HIP9011_06 INTERSIL [Intersil Corporation], HIP9011_06 Datasheet - Page 5

• Manufacturer Part Number: HIP9011_06
• Description: Engine Knock Signal Processor
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Diagrams
SYMBOL
SYMBOL
t
t
t
CSCH
t
SCCH
CSCF
t
t
t
t
PWH
t
PWL
SUH
t
CSH
SUL
t
CIH
HH
HL
t1
t2
t3
t4
Minimum time from CS falling edge to SCK rising edge.
Minimum time from CS falling edge to SCK falling edge.
Minimum time for the SCK low.
Minimum time for the SCK high.
Minimum time from SCK falling after 8 bits to CS raising edge.
Minimum time from data high to falling edge of spiclk.
Minimum time from data low to falling edge of spiclk.
Minimum time for data high after the falling edge of the spiclk.
Minimum time for data low after the falling edge of the spiclk.
Minimum time after CS raises until INT/HOLD goes high.
Minimum time between programming 2 internal registers.
Maximum rise time of the INT/HOLD signal.
Maximum time after INT/HOLD rises for INTOUT to begin to integrate.
Maximum fall time of INT/HOLD signal.
Typical time after INT/HOLD goes low before chip goes into hold state.
5
t
CSCH
SCK
SI
SO
t
INT/HOLD
CS
CSCF
t
SUH
INT/HOLD
INTOUT
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS
t1
t2
t
CSH
B7
B7
TABLE 1. SPI TIMING REQUIREMENTS
B6
B6
t
FIGURE 2. INTEGRATOR TIMING
t
HH
PWH
B5
B5
FIGURE 1. SPI TIMING
B4
B4
HIP9011
t
PWL
REQUIREMENT
REQUIREMENT
B3
B3
B2
t3
B2
t4
t
SCCH
B1
B1
B0
t
B0
CIH
200ns
TIME
TIME
10ns
80ns
60ns
60ns
80ns
20ns
20ns
10ns
10ns
45ns
20µs
45ns
20µs
January 6, 2006
8µs
FN4367.2