MAX4358ECE MAXIM [Maxim Integrated Products], MAX4358ECE Datasheet - Page 31

• Manufacturer Part Number: MAX4358ECE
• Description: 32 x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers
• Manufacturer: MAXIM [Maxim Integrated Products]

SCLK is the serial-data clock which clocks data into the
data input registers (Figure 3). Data at DIN is loaded in
at each falling edge of SCLK. DOUT is the data shifted
out of the 112-bit Complete Matrix Mode register (Mode
= 1). DIN passes directly to DOUT when in Individual
Output Address Mode (Mode = 0).
The falling edge of UPDATE latches the data and pro-
grams the matrix. When using Individual Output
Address Mode, the address recognition output AOUT
drives low when control-word bits D14 to D11 match
the address programming inputs (A3–A0) and UPDATE
is low (Table 1). Table 1 is the operation truth table.
The MAX4358 offers two programming modes:
Individual Output Address Mode and Complete Matrix
with On-Screen Display Insertion and I/O Buffers
Figure 2. Serial Interface Block Diagram
32 x 16 Nonblocking Video Crosspoint Switch
______________________________________________________________________________________
Programming the Matrix
DIN
MODE
SCLK
CE
MODE
SCLK
CE
OUTPUT ADDRESS DECODE
EN
UPDATE
SWITCH MATRIX
16-BIT INDIVIDUAL OUTPUT
112-BIT COMPLETE MATRIX MODE REGISTER
ADDRESS MODE REGISTER
CHIP ADDRESS
512
11
11
112-BIT PARALLEL LATCH
A0–A3
SWITCH DECODE
7
Mode. These two distinct programming modes are
selected by toggling a single MODE pin high or low.
Both modes operate with the same physical board lay-
out. This flexibility allows initial programming of the IC
by daisy-chaining and sending one long data word
while still being able to immediately address and
update individual outputs in the matrix.
Drive MODE to logic low to select Mode 0. Individual
outputs are programmed via the serial interface with a
single 16-bit control word. The control word consists of
a don’t care MSB, the chip address bits, output
address bits, an output enable/disable bit, an output
gain-set bit, and input address bits (Table 2 through
Table 6, and Figure 2).
4
4
112
7
Individual Output Address Mode (MODE = 0)
MODE
OUTPUT ENABLE
16
1
112
AOUT
112
MODE
B
A
ROUTING
DATA
GATE
S
MODE
DOUT
31