AD8197B-EVALZ AD [Analog Devices], AD8197B-EVALZ Datasheet

Page 1

... TMDS input termination resistors via I impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. The AD8197B is provided in a 100-lead LQFP, Pb-free, surface- mount package, specified to operate over the −40°C to +85°C temperature range. PRODUCT HIGHLIGHTS GAME CONSOLE 1 ...

Page 2

... AD8197B TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Typical Application........................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Input Channels............................................................................ 13 Output Channels ........................................................................ 13 Auxiliary Switch ...

Page 3

... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev Page AD8197B Min Typ Max Unit 2.25 Gbps − (p-p) ...

Page 4

... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8197B output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. ...

Page 5

... AVCC + 0.6 V 100-Lead LQFP 5.5 V 2.2 W MAXIMUM POWER DISSIPATION AVCC − 1.4 V < V < IN The maximum power that can be safely dissipated by the AD8197B AVCC + 0 limited by the associated rise in junction temperature. The 2.0 V maximum safe junction temperature for plastic encapsulated DVEE − 0.3 V < V < IN AMUXVCC + 0.6 V devices is determined by the glass transition temperature of the DVEE − ...

Page 6

... IN_B3 12 IP_B3 14 IN_A0 15 IP_A0 17 IN_A1 18 IP_A1 20 IN_A2 21 IP_A2 AD8197B TOP VIEW (Not to Scale) Figure 3. Pin Configuration 1 Type Description Power Positive Analog Supply. 3.3 V nominal High Speed Input Complement High Speed Input. Power Negative Analog Supply nominal High Speed Input Complement. ...

Page 7

... Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. Power Positive Auxiliary Multiplexer Supply typical. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. Rev Page AD8197B ...

Page 8

... AD8197B Pin No. Mnemonic 89 AUX_COM1 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 Type Description LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. ...

Page 9

... Figure 7. Rx Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 8. Rx Eye Diagram at TP3 (Cable = 20 meters, 24 AWG) Rev Page − 1, data rate = 2.25 Gbps, unless AD8197B SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP2 TP3 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps AD8197B ...

Page 10

... TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted. REFERENCE EYE DIAGRAM AT TP1 0.125UI/DIV AT 2.25Gbps Figure 10. Tx Eye Diagram at TP2 0.125UI/DIV AT 2.25Gbps Figure 11. Tx Eye Diagram at TP2 AD8197B DIGITAL EVALUATION PATTERN BOARD GENERATOR SMA COAX CABLE ...

Page 11

... PE MAX 0.2 0.1 1.65Gbps, PE MAX HDMI CABLE LENGTH (m) 1200 1000 800 600 400 200 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 DATA RATE (Gbps) Figure 18. Eye Height vs. Data Rate 800 700 600 500 400 300 200 100 0 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V) Figure 19. Eye Height vs. Supply Voltage AD8197B 15 20 2.0 2.2 2.4 3.4 3.5 3.6 ...

Page 12

... AD8197B T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted (p- (rms 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (V) Figure 20. Jitter vs. Differential Input Swing ...

Page 13

... INTRODUCTION The AD8197B is a pin-to-pin HDMI 1.3 receive-compliant replacement for the AD8197A. The primary function of the AD8197B is to switch one of four (HDMI or DVI) single link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single- ended, low speed control signals ...

Page 14

... DDC bus, regardless of the state of the AD8197B and any downstream circuit. For this configuration, the auxiliary inputs of the powered down AD8197B need high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus. ...

Page 15

... SERIAL CONTROL INTERFACE RESET On initial power-up any point in operation, the AD8197B register set can be restored to the status of the parallel control interface pins and some preprogrammed default values by pulling the RESET pin to low, in accordance with the specifica- tions in Table 1. During normal operation, however, the RESET pin must be pulled ...

Page 16

... This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8197B to acknowledge the request. 11. The AD8197B serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Acknowledge the data from the AD8197B. ...

Page 17

... PARALLEL CONTROL INTERFACE The AD8197B can be partially controlled through the parallel interface using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 18 ...

Page 18

... The serial interface configuration registers can be read and written using the I The least significant bits of the AD8197B I to 3.3 V (Logic (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197B is reset as described in the Serial Control Interface section. 2 Table 5. Serial (I ...

Page 19

... RX_EQ[X] Corresponding Input TMDS Channel Bit 0 B0 Bit 1 B1 Bit 2 B2 Bit 3 B3 Bit 4 A0 Bit 5 A1 Bit 6 A2 Bit 7 A3 Bit 8 C3 Bit 9 C2 Bit 10 C1 Bit 11 C0 Bit 12 D3 Bit 13 D2 Bit 14 D1 Bit 15 D0 Rev Page AD8197B ...

Page 20

... AD8197B TRANSMITTER SETTINGS REGISTER TX_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis Level Select Bus (For All TMDS Channels) Table 15. TX_PE[1:0] Description TX_PE[1:0] Description 00 No pre-emphasis (0 dB) 01 Low pre-emphasis (2 dB) 10 Medium pre-emphasis (4 dB) 11 High pre-emphasis (6 dB) TX_PTO: High Speed (TMDS) Output Termination On/Off Select Bit (For All Channels) Table 16 ...

Page 21

... Because most systems use serial control for the input termination resistors, the parallel control interface is limited to controlling the AD8197B status after reset and before serial logic control. The state of each pin is set by tying it to 3.3 V (Logic (Logic 0). Table 18. Parallel Interface Register Map ...

Page 22

... AD8197B HIGH SPEED DEVICE MODES REGISTER PP_EN: High Speed (TMDS) Channels Enable Bit Table 19. PP_EN Description PP_EN Description 0 High speed channels off, low power/standby mode 1 High speed channels on PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus Table 20. PP_CH Mapping PP_CH[1:0] O[3:0] Description ...

Page 23

... APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197B Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197B is an HDMI/DVI switch, featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1 ...

Page 24

... TMDS traces is more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8197B, all four high speed signals should be routed on a PCB in accor- dance with the same RF layout guidelines. ...

Page 25

... Ground Current Return In some applications, it can be necessary to invert the output pin order of the AD8197B. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers necessary to also reroute the corresponding reference plane in order to provide one continuous ground current return path for the differential signals ...

Page 26

... AD8197B the AD8197B and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the PCB ...

Page 27

... RECOMMENDED NOT RECOMMENDED Figure 34. Recommended Pad Outline for Bypass Capacitors In applications where the AD8197B is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF capacitors ...

Page 28

... ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD8197BASTZ −40°C to +85°C AD8197BASTZ-RL 1 −40°C to +85°C 1 AD8197B-EVALZ RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1.60 MAX 0.75 100 1 0.60 0.45 PIN 1 0 ...