TH8061KDCA MELEXIS [Melexis Microelectronic Systems], TH8061KDCA Datasheet - Page 17

• Manufacturer Part Number: TH8061KDCA
• Description: Voltage Regulator with integrated LIN Transceiver
• Manufacturer: MELEXIS [Melexis Microelectronic Systems]

3.6 LIN BUS Transceiver
The TH8061 is a bi-directional bus interface device for data transfer between LIN bus and the LIN protocol
controller.
The transceiver consists of a pnp-driver (1.2V@40mA) with slew rate control, wave shaping and current
limitation and a receiver with high voltage comparator followed by a debouncing unit.
Transmit Mode
During transmission the data at the pin TxD will be transferred to the BUS driver to generate a bus signal. To
minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control
and wave shaping unit.
Transmitting will be interrupted in the following cases:
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode
This diode prevents the reverse current of V
(V
No additional termination resistor is necessary to use the TH8061 in LIN slave nodes. If this IC is used for
LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in series with a
diode to VBAT.
Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit (τ = 2.8µs).
The receive threshold values V
hysteresis of 0.135*V
0.6*V
Datarate
The TH8061 is a constant slew rate transceiver which means that the bus driver works with a fixed slew
rate range of 1.0 V/µs ≤ ∆V/∆T ≤ 2.5V/µs. This principle secures a very good symmetry of the slope times
between recessive to dominant and dominant to recessive slopes within the LIN bus load range (C
The TH8061 guarantees data rates up to 20kbit within the complete bus load range under worst case
conditions. The constant slew rate principle is very robust against voltage drops and can operate with RC-
oscillator systems with a clock tolerance up to ±2% between 2 nodes.
TH8061 – Datasheet
3901008061
BUS
-
-
-
>V
SUP
Sleep mode
Thermal Shutdown active
Master Reset (V
SUP
will be securely observed.
).
BUS
RxD
VSUP
60%
50%
40%
SUP
CC
. Including all tolerances the LIN specific receive threshold values of 0.4*V
< 3.15V)
V
V
thr_min
thr_max
Figure 12 - Receive mode impulse diagram
thr_max
V
thr_hys
and V
Voltage Regulator with integrated LIN Transceiver
t < t
V
thr_min
thr_cnt
deb_BUS
Page 17 of 36
BUS
are symmetrical to the centre voltage of 0.5*V
during differential voltage between VSUP and BUS
t < t
deb_BUS
TH8061
BUS
SUP
June 2004
SUP
, R
Rev 007
with a
term
and
).