LMH6552MA NSC [National Semiconductor], LMH6552MA Datasheet - Page 14

• Manufacturer Part Number: LMH6552MA
• Description: 1 GHz Fully Differential Amplifier
• Manufacturer: NSC [National Semiconductor]

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SPLIT SUPPLY OPERATION
For optimum performance, split supply operation is recom-
mended using +5V and −5V supplies however operation is
possible on split supplies as low as +2.25V and −2.25V and
as high as +6V and −6V. Provided the total supply voltage
does not exceed the 4.5V to 12V operating specification, non
symmetric supply operation is also possible and in some cas-
es advantageous. For example , if a 5V DC coupled operation
is required for low power dissipation but the amplifier input
common mode range prevents this operation, it is still possi-
ble with split supplies of (V
and V
mon mode range to suit the application.
OUTPUT NOISE PERFORMANCE AND MEASUREMENT
Unlike differential amplifiers based on voltage feedback ar-
chitectures, noise sources internal to the LMH6552 refer to
the inputs largely as current sources, hence the low input re-
ferred voltage noise and relatively higher input referred cur-
rent noise. The output noise is therefore more strongly
coupled to the value of the feedback resistor and not to the
closed loop gain, as would be the case with a voltage feed-
back differential amplifier. This allows operation of the
LMH6552 at much higher values of gain without incurring a
substantial noise performance penalty, simply by choosing a
suitable feedback resistor.
Figure 6 shows a circuit configuration used to measure noise
figure for the LMH6552 in a 50Ω system. A R
275Ω is chosen to minimize output noise while simultaneous-
ly allowing both high gain (9 V/V) and proper 50Ω input
termination. Refer to the section titled Single Ended Input Op-
eration for calculation of resistor and gain values. Noise figure
values at various frequencies are shown in the plot titled
Noise Figure in the Typical Performance Characteristics sec-
tion.
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters present challenging load condi-
tions. They typically have high impedance inputs with large
and often variable capacitive components. As well, there are
usually current spikes associated with switched capacitor or
sample and hold circuits. Figure 7 shows a combination circuit
of the LMH6552 driving the ADC12DL080. The two 125Ω re-
sistors serve to isolate the capacitive loading of the ADC from
the amplifier and ensure stability. In addition, the resistors,
along with a 2.2 pF capacitor across the outputs (in parallel
with the ADC input capacitance), form a low pass anti-aliasing
filter with a pole frequency of about 60 MHz. For switched
+
FIGURE 6. Noise Figure Circuit Configuration
and V
−
are selected to center the amplifier input com-
+
) and (V
−
). Where (V
+
) - (V
F
value of
−
) = 5V
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capacitor input ADCs, the input capacitance will vary based
on the clock cycle, as the ADC switches between the sample
and hold mode. See your particular ADC's data sheet for de-
tails.
Figure 8 shows the SFDR and SNR performance vs. frequen-
cy for the LMH6552 and ADC12DL080 combination circuit
with the ADC input signal level at −1 dBFS. The ADC12DL080
is a dual 12-bit ADC with maximum sampling rate of 80 MSPS.
The amplifier is configured to provide a gain of 2 V/V in single
to differential mode. An external band-pass filter is inserted in
series between the input signal source and the amplifier to
reduce harmonics and noise from the signal generator. In or-
der to properly match the input impedance seen at the
LMH6552 amplifier inputs, R
proper input balance.
The amplifier and ADC should be located as close as possi-
ble. Both devices require that the filter components be in close
proximity to them. The amplifier needs to have minimal par-
asitic loading on the output traces and the ADC is sensitive to
high frequency noise that may couple in on its input lines.
Some high performance ADCs have an input stage that has
a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage
mixing down into the first Nyquist zone (DC to Fs/2).
The LMH6552 is capable of driving a variety of National Semi-
conductor Analog to Digital Converters. This is shown in
Table 2, which offers a complete list of possible signal path
FIGURE 8. LMH6552/ADC12DL080 SFDR and SNR
Performance vs. Frequency
FIGURE 7. Driving an ADC
M
is chosen to match Z
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|| R
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for