ISL8033A INTERSIL [Intersil Corporation], ISL8033A Datasheet - Page 4

• Manufacturer Part Number: ISL8033A
• Description: Dual 3A Low Quiescent Current High Efficiency Synchronous Buck Regulator
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Configuration
Pin Descriptions
PIN NUMBER
22, 23
1, 24
7, 8
10
11
12
13
4
9
5
6
SYMBOL
PGND2
SGND
SYNC
EN2
PG2
PG1
EN1
LX2
FB2
FB1
NC
4
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the
VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT2 voltage.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the
transconductance error amplifier. The output voltage is set by an external resistor divider
connected to FB2. With a properly selected divider, the output voltage can be set to any voltage
between the power rail (reduced by converter losses) and the 0.8V reference. There is an internal
compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor
the Channel 2 regulator output voltage.
No connect pins. Please tie to GROUND.
The feedback network of the Channel 1 regulator. FB1 is the negative input to the
transconductance error amplifier. The output voltage is set by an external resistor divider
connected to FB1. With a properly selected divider, the output voltage can be set to any voltage
between the power rail (reduced by converter losses) and the 0.8V reference. There is an
internal compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor
the Channel 1 regulator output voltage.
System ground. Make a single point connection from these pins to PGND.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT1 voltage.
Connect to logic high or input voltage VIN. Connect to an external function generator for external
Synchronization. Negative edge trigger. Do not leave this pin floating. Do not tie this pin low
(or to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the
VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating.
VIN2
VIN2
EN2
PG2
FB2
LX2
ISL8033, ISL8033A
1
2
3
4
5
6
24
7
ISL8033, ISL8033A
23
8
(24 LD QFN)
TOP VIEW
22
9
25
PD
10
21
11
20
DESCRIPTION
12
19
18
17
16
15
14
13
LX1
VIN1
VIN1
VDD
ISET
EN1
October 21, 2010
FN6854.1