ISL6425 INTERSIL [Intersil Corporation], ISL6425 Datasheet
ISL6425
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ISL6425 Summary of contents
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... Voltage Regulator with I C Interface for Advanced Satellite Set-top Box Designs The ISL6425 is a highly integrated solution for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise block (LNB). This device is comprised of a current-mode boost PWM and a low-noise ...
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... Pinout SEL18V BYPASS 2 ISL6425 ISL6425 (32 LEAD 5x5 QFN) TOP VIEW PGND SGND PGND 7 GATE CPSWOUT AGND 20 VOUT 19 DSQIN 18 TCAP FN9176.1 February 8, 2005 ...
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... D2 L3 4.7uH 1 C4 C13 STPS2L40U 56uF 10uF 0 0 C16 0 1uF 0 C18 1n 1 PGND CPSWOUT SGND SEL18V NC 5 ISL6425ER NC AGND C8 1uF 6 BYP VOUT 7 PGND DSQIN 8 GATE TCAP C9 1.5n R8 68K 0 C10 33p 2 D5 C14 C15 10uF 10uF 0 0 C17 47nF ...
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Block Diagram OVERCURRENT COUNTER PROTECTION LOGIC SCHEME 1 PWM LOGIC GATE PGND E PAD ILIM CS AMP CS ∑ 11 COMPENSATION COMP VSW 14 VOUT 20 ON CHIP VCC 28 LINEAR UVLO SGND POR ...
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... TONE Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time 5 ISL6425 Thermal Information Thermal Resistance QFN Package (Notes Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C Maximum Lead Temperature (Soldering 10s 300°C NOTE: The device junction temperature should be kept below 150° ...
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... Voltage programming signals VSEL and LLC are implemented via the 450mA. 5. Guaranteed by Design. 6. Unused DSQIN pin should be connected to GND. SEL18V pins is internally connected to GND by a 200K resistor. 6 ISL6425 = -20°C to +85°C, unless otherwise noted. Typical values are 12mA, unless otherwise noted. See software description section for I OUT ...
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... SEL18V When connected HIGH, this pin will change the output of the PWM to 18V. Functional Description The ISL6425 single output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for a low noise block (LNB) are available simultaneously in any output configuration ...
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... When the bus is free, both lines are HIGH. The output stage of ISL6425 will have an open drain/open collector in order to perform the wired-AND function. Data on the I transferred up to 100kbits/s in the standard-mode 400kbits/s in the fast-mode. The level of logic “ ...
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... SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6425 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. SCL ...
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... Received Data ( Bus Read Mode The ISL6425 can provide to the master a copy of the System 2 Register information via the I C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set the following Master generated clock bits, the ISL6425 issues a byte on the SDA data bus line (MSB transmitted first) ...
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... Connecting this pin to GND forces the chip I address to 0001000; applying a voltage >2.7V forces the address to 0001001, as shown below. TABLE 7. ADDRESS PIN CHARACTERISTICS VADDR MIN Vaddr-1 0V “0001000” Vaddr-2 2.7V “0001001” 11 ISL6425 Electrical Characteristics 2 C PARAMETER Input Logic High, VIH Input Logic Low, VIL Input Logic Current, IIL ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL6425 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...