ISL6422 INTERSIL [Intersil Corporation], ISL6422 Datasheet - Page 9

• Manufacturer Part Number: ISL6422
• Description: Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Pin Descriptions
SDA
SCL
VSW1 and VSW2
PGND1 and PGND2
CS1 and CS2
SGND
TCAP1 and TCAP2
BYP
TXT1 and TXT2
VCC
GATE1 and GATE2
VOUT1 and VOUT2
ADDR0 and ADDR1
EXTM1 and EXTM2
FLT
CPVOUT, CPSWIN,
CPSWOUT
SELVTOP1 and
SELVTOP2
TDIN1 and TDIN2
TDOUT1 and TDOUT2
AGND
SYMBOL
Bidirectional data from/to I
Clock from I
Input of the linear post-regulator.
Dedicated ground for the output gate driver of respective PWM.
Current sense input; connect the sense resistor Rsc at this pin for desired overcurrent value for respective PWM.
Small signal ground for the IC.
Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.22µF.
Bypass capacitor for internal 5V.
TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV
max for the Rx mode when the TXT1 and TXT2 are set low. The threshold is 400mV min in the Tx mode when TXT1
and TXT2 are set high. If Tx/Rx mode is set by I
(5V) by an on-chip driver.
Main power supply to the chip.
These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of
driving the gate of a power FET. These outputs are actively held low when V
Output voltage for LNB A and LNB B respectively.
Address pins select four different device addresses per Table 19.
These pins can be used in two ways:
1. As an input for externally modulated Diseqc tone signal that is transferred symmetrically onto V
2. Alternatively apply a Diseqc modulation envelope that modulates an internal tone and then transfers it symmetrically
This is an open drain output from the controller. When the FLT goes low, it indicates that an Over Temperature has
occurred. The processor should then look at the I
indicates that the device is functioning normally.
A 47nF charge pump cap is connected to CPVOUT. Connect a 1.5nF capacitor between CPSWIN and CPSWOUT.
The following description applies to both pins and both bits.
When this pin is low, the V
When this pin is high, the 18V/19V range is selected by the I
The voltage select pin voltage VSPEN1 and VSPEN2 I
to be active. Setting VSPEN1 and VSPEN2 high disables these pins and voltage selection will be done using the I
bits VBOT1 and VBOT2 and VTOP1 and VTOP2 only.
TDIN1 and TDIN2 are the tone decoder inputs for channels 1 and 2.
TDOUT1 and TDOUT2 are the tone detector outputs for channels 1 and 2. TDOUT1 and TDOUT2 are open drain
outputs.
Analog ground for the IC.
onto V
9
OUT
2
C bus.
.
2
OUT
C bus.
is in the 13V/14V range selected by the I
ISL6422
2
C bit TTH(1 ,2), when TTH(1, 2) = 1, then TXT(1, 2) will be driven high
2
C register to get the actual cause of the error. A high on the FLT
FUNCTION
2
C bit must be set low for the SELVTOP1 and SELVTOP2 pins
2
C bit VTOP1 and VTOP2.
2
C bit VBOT1 and VBOT2.
CC
is below the UVLO threshold.
OUT
.
April 10, 2007
FN9190.1
2
C