AT89C51RB2-RLTCM ATMEL [ATMEL Corporation], AT89C51RB2-RLTCM Datasheet - Page 42
AT89C51RB2-RLTCM
Manufacturer Part Number
AT89C51RB2-RLTCM
Description
8-bit Microcontroller with 16K/ 32K Bytes Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51RB2-RLTCM.pdf
(125 pages)
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Serial I/O Port
Framing Error Detection
42
AT89C51RB2/RC2
The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates.
Serial I/O port includes the following enhancements:
•
•
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (see Figure 16).
Figure 16. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (see Table 33) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (see Figure 17 and Figure 18).
Figure 17. UART Timings in Mode 1
SMOD0 = X
SMOD0 = 1
SMOD1
SM0/FE
Framing error detection
Automatic address recognition
RXD
FE
RI
SMOD0
SM1
Start
bit
SM2
-
D0
REN
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
POF
To UART framing error control
D1
TB8
GF1
D2
RB8
GF0
D3
Data Byte
D4
PD
TI
D5
IDL
RI
D6
SCON (98h)
PCON (87h)
D7
Stop
bit
4180B–8051–04/03
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