ISL6322 INTERSIL [Intersil Corporation], ISL6322 Datasheet - Page 33

• Manufacturer Part Number: ISL6322
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

quiescent current with no load at both drive outputs; N
and N
phase, respectively; N
phases. The I
controller without capacitive load and is typically 75mW at
300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
power will be dissipated by the external gate resistors (R
P
P
P
R
P
DR_UP
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
DR
DR_UP
DR_LOW
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
EXT1
PVCC
BOOT
PVCC
=
Q2
P
=
, and in the boot strap diode, P
=
DR_UP
=
are the number of upper and lower MOSFETs per
PHASE
R
=
P
---------------------
R
⎛
⎜
⎝
R
G1
LO2
Qg_Q1
--------------------------------------
R
BOOT
HI2
⎛
⎜
⎝
R
Q*
R
HI1
--------------------------------------
R
3
LO1
+
HI1
HI2
+
VCC product is the quiescent power of the
R
-------------
R
N
+
P
GI1
DR_UP
HI1
Q1
R
R
+
DR_LOW
HI2
EXT1
R
LGATE
EXT2
PHASE
UGATE
, the lower drive path resistance,
+
+
--------------------------------------- -
R
+
33
LO1
--------------------------------------- -
R
P
R
is the number of active
LO2
BOOT
EXT2
R
R
G2
R
+
LO1
R
G
G1
+
R
LO2
G
EXT1
R
+
=
R
C
EXT2
GI2
(
GD
BOOT
R
R
C
I
C
Q
GI1
GD
G2
GS
⎞ P
⎟
⎠
C
⋅
VCC
⋅
⎞ P
⎟
⎠
GS
+
---------------------
. The rest of the
⋅
S
Qg_Q1
---------------------
R
-------------
N
Qg_Q2
GI2
S
3
Q2
)
2
D
D
Q2
C
(EQ. 31)
Q1
DS
Q1
C
DS
G1
ISL6322
and R
the MOSFETs. Figures 19 and 20 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P
estimated with Equation 31.
Inductor DCR Current Sensing Component
Selection
The ISL6322 senses each individual channel’s inductor
current by detecting the voltage across the output inductor
DCR of that channel (as described in “Continuous Current
Sampling” on page 13). As Figure 21 illustrates, an R-C
network is required to accurately sense the inductor DCR
voltage and convert this information into a current, which is
proportional to the total output current. The time constant of
this R-C network must match the time constant of the
inductor L/DCR.
The R-C network across the inductor also sets the
overcurrent trip threshold for the regulator. Before the R-C
components can be selected, the desired overcurrent
protection level should be chosen. The minimum overcurrent
trip threshold the controller can support is dictated by the
DCR of the inductors and the number of active channels. To
calculate the minimum overcurrent trip level, I
Equation 32, where N is the number of active channels, and
DCR is the individual inductor’s DCR.
The overcurrent trip level of the ISL6322 cannot be set any
lower then the I
minimum overcurrent trip level is desired, do the
I
OCP min
MOSFET
DRIVER
,
ISL6322 INTERNAL CIRCUIT
G2
SAMPLE
FIGURE 21. DCR SENSING CONFIGURATION
) and the internal gate resistors (R
=
I
n
0.0375 N
-------------------------- -
DCR
OCP,min
UGATE(n)
LGATE(n)
I
SEN
⋅
+
-
level calculated above. If the
V
R
V
IN
ISEN
C
(s)
-
DR
R
INDUCTOR
1
L
, can be roughly
V
ISEN-(n)
ISEN+(n)
L
I
(s)
L
V
C
DCR
GI1
*R
-
R
(s)
C
2*
1
2
OCP,min
-
is OPTIONAL
and R
August 21, 2006
C
V
GI2
OUT
(EQ. 32)
, use
FN6328.0
OUT
) of