ISL6251 INTERSIL [Intersil Corporation], ISL6251 Datasheet - Page 17

• Manufacturer Part Number: ISL6251
• Description: Low Cost Multi-Chemistry Battery Charger Controller
• Manufacturer: INTERSIL [Intersil Corporation]

The voltage gain with open current loop is:
Where
error amplifier. The Voltage loop gain with current loop
closed is given by:
If T
From the above equation, it is shown that the system is a
single order system, which has a single pole located at
before the half switching frequency. Therefore, simple type II
compensator can be easily used to stabilize the system.
Figure 15 shows the voltage loop compensator, and its
transfer function is expressed as follows:
T
L
L
v
v
v
FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS
+
+
(
(
(
i
S
S
(S)>>1, then it can be simplified as follows:
S
i ˆ
i ˆ
v ˆ
v ˆ
in
in
in
in
)
)
)
=
=
=
K =
KF
1
V
FIGURE 15. VOLTAGE LOOP COMPENSATOR
V
T
+
FB
o
m
v
T
V
( )
F
V
I
I
i
S
L
L
FB
R
1
( )
d ˆ
d ˆ
o
S
BUCK REGULATOR
Fm
Fm
( ) ( )
o
+
+
S
R
, V
+
1:D
1:D
d ˆ
d ˆ
T
A
R
v
FB
L
Vo
Vo
Vo
Vo
S
1
V
V
V
V
V
V
1
is the feedback voltage of the voltage
+
in
in
REF
REF
FB
FB
+
He(S)
He(S)
d ˆ
d ˆ
ω
ω
S
esr
S
p
-
-
-
-
+
+
+
+
i ˆ
i ˆ
17
L
L
g
g
T
T
m
m
H
A
i
i
(S)
(S)
v
e
L
L
v ˆ
v ˆ
( )
( )
S
S
comp
comp
C1
C1
R1
R1
,
V
V
R
R
ω
COMP
COMP
T
T
-Av(S)
-Av(S)
p
≈
R
o
1
Rc
Rc
Co
Co
C
Ro
Ro
o
T
T
v
v
(S)
(S)
ISL6251, ISL6251A
v ˆ
v ˆ
o
o
ω
K
K
p
where
Compensator design goal:
• High DC gain
• Loop bandwidth f
• Gain margin: >10dB
• Phase margin: 40°
The compensator design procedure is as follows:
The loop gain T
gain. Therefore, the compensator resistance R
determined by:
where g
amplifier. Compensator capacitor C1 is then given by:
Example: V
C
V
R
1.5kHz. The compensator capacitor is C
choose voltage loop compensator: R
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
C
R
A
1. Put compensator zero at:
2. Put one compensator pole at zero frequency to achieve
1. Top Layer: signal lines, or half board for signal lines and
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
PWM
1
o
1
v
1
=10 µ F/10m Ω , L=10 µ H, g
=8.0k Ω . Choose R
( )
=
=
S
high DC gain, and put another compensator pole at either
ESR zero frequency or half switching frequency,
whichever is lower.
the other half board for power lines
Power traces
ω
R
2
cz
=
π
=V
1
ω
1
m
v ˆ
ω
f
g
cz
=
c
v ˆ
comp
IN
m
cz
V
is the trans-conductance of the voltage loop error
FB
(
1 −
o
V
=
/11, f
in
C
FB
=19V, V
R
o
3
1
=
R
1
C
)
v
c
T
g
(S) at cross over frequency of f
1
R
=20kHz, then compensator resistance
m
o
,
1
c
C
1
:
o
o
1
+
SC
=16.8V, I



=10k Ω . Put the compensator zero at
1
5
ω
1
S
cz
−
20
1
m
=250 µ s, R



f
o
s
=2.6A, f
1
=10K, C
T
s
1
=300kHz,
=0.2 Ω , V
=10nF. Therefore,
1
1
=10nF.
c
is
has unity
FB
June 17, 2005
=2.1V,
FN9202.1