DP84902M NSC [National Semiconductor], DP84902M Datasheet - Page 2

• Manufacturer Part Number: DP84902M
• Description: 1,7 Encoder/Decoder Circuit
• Manufacturer: NSC [National Semiconductor]

Power Supply and Ground Pins
Input Pin Descriptions
ECLV
V
V
CRC
CRD
CRL S
ERASE
RESET
RG
SYNCCLK
SYNCDATA
WCLK
WG
Connection Diagram
Pin Descriptions
DD
SS
Symbol
CC
Pin
11
20
19
12
13
17
18
8
1
5
4
3
2
ECLV
V
V
CONTROL REGISTER CLOCK Positive-edge-active control register clock input
CONTROL REGISTER DATA Control register data input
CONTROL REGISTER LATCH SHIFT A logical low state applied to this input allows the CONTROL
REGISTER CLOCK input to clock data into the control register’s shift register via the CONTROL
REGISTER DATA input A logical high state latches the data into a bank of latches and issues the
information to the appropriate circuitry within the ENDEC
ERASE This active high input is used while in the write mode to force a logical low at the CODEOUT
output (or a logical high if CODEOUT is inverted) This is useful to blank out (DC erase which issues no
transitions) a track for analog flaw map tesing
RESET A logical low level applied to this input forces the ENDEC to a power-on-reset state and
presets its control register to predetermined operating setup conditions During normal operation this
pin must be held at a logical high level
READ GATE This input accepts a mode control signal from the controller for the decoder It permits
the reading of data from the disk when at a logical high level It inhibits reading and resets the decoder
state machine when at a logical low level There are no set-up or hold timing requirements for the
enabling or disabling of this input
SYNCHRONIZED CLOCK This input accepts the code rate (1 5F) synchronized clock signal from the
read channel’s data synchronizer This signal is used to clock the synchronized data into the decoder
on the negative edge of SYNCCLK in the read mode and is the source clock for clocking codeout data
from the encoder during the write mode
SYNCHRONIZED DATA This input accepts the synchronized data signal MSB first from the read
channel’s data synchronizer for the decoder’s use
WRITE CLOCK This input is used only in the external write clock mode The write clock signal (Note 1)
from the controller is used to strobe the NRZ input data into the ENDEC The write clock signal from the
controller must be the RRCLK echoed by the controller If the external write clock mode is not selected
this pin should be tied to V
WRITE GATE This input accepts a mode control signal from the controller for the encoder It permits
the writing of a header and data to the disk when at a logical high level It inhibits writing and resets the
encoder state machine when at a logical low level There are no set-up or hold timing requirements for
the enabling or disabling of this input
DD
SS
Supply Pin 5V
Ground reference
CC
Supply Pin 5V
See NS Package Number M20B or MSA20
Order Number DP84902M or DP84902MS
g
10%
FIGURE 2 DP84902 Pinout
g
10%
DD
or V
SS
2
Functional Description
TL F 11963– 2