DP8473N NSC [National Semiconductor], DP8473N Datasheet - Page 4

• Manufacturer Part Number: DP8473N
• Description: DP8473 Floppy Disk Controller PLUS-2
• Manufacturer: NSC [National Semiconductor]

MTR0
MTR1
MTR2
MTR3
OSC1
OSC2 CLOCK
PUMP PREN
RD
RDATA
RESET
RPM LC
SETCUR
STEP
TC
TRK0
WDATA
WGATE
WR
WRT PRT
V
V
Pin Descriptions
CC
CCA
Symbol
DP8473
PCC
52
38
37
46
17
44
15
51
48
50
33
10
49
16
12
14
13
8
7
1
3
(Continued)
DP8473
DIP
36
35
42
15
41
13
47
44
46
31
45
14
10
12
11
6
5
8
1
This is an active low motor enable line for drive 0 which is controlled by the Drive Control
register This is a high drive open drain output
This is an active low motor enable line for drive 1 Similar to MTR0
This is an active low motor enable line for drive 2 Similar to MTR0
This is an active low motor enable line for drive 3 Similar to MTR0
One side of an external 24 MHz crystal is attached here This pin is tied low if an external
clock is used
One side of the external 24 MHz crystal is attached here If a crystal is not used a TTL or
CMOS compatible clock is connected to this pin
When the PU bit is set in Mode Command this pin is an output that indicates when the
charge pump is making a correction Otherwise this pin is an input that sets the precomp
mode as shown in Table VI If pin is configured as PUMP PREN is assumed high
Active low input to signal a read from the controller to the microprocessor
The active low raw data read from the disk is connected here This is a Schmitt input
Active high input that resets the controller to the idle state and resets all the output lines
to the disk drive to their disabled state The Drive Control register is reset to 00 The Data
Rate register is set to 250 kb s The Specify command registers are not affected The
Mode Command registers are set to the default values Reset should be held active
during power up To prevent glitches activating the reset sequence a small capacitor
(1000 pF) should be attached to this pin
This high drive open drain output pin has two functions based on the selection of the
DRVTYP pin
1 When using a dual speed spindle motor floppy drive (DRVTYP pin low) this output is
used to select the spindle motor speed either 300 RPM or 360 RPM In this mode this
output goes low when 250 300 kb data rate is chosen in the data rate register and high
when 500 kb s is chosen
2 When using a single speed spindle motor floppy drive (DRVTYP pin high) this pin
indicates when to reduce the write current to the drive This output is high for high density
media (when 500 kb s is chosen)
An external resistor connected from this pin to analog ground programs the amount of
charge pump current that drives the external filters The PLL Filter Design section shows
how to determine the values
This active low open drain high drive output will produce a pulse at a software
programmable rate to move the head during a seek operation
Active high input to indicate the termination of a DMA transfer This signal is enabled
when the DMA Acknowledge pin is active
This active low Schmitt input tells the controller that the head is at track zero of the
selected disk drive
This is the active low open drain write precompensated serial data to be written onto the
selected disk drive This is a high drive open drain output
This active low open drain high drive output enables the write circuitry of the selected
disk drive This output has been designed to prevent glitches during power up and power
down This prevents writing to the disk when power is cycled
Active low input to signal a write from the microprocessor to the controller
This active low Schmitt input indicates that the disk is write protected Any command that
writes to that disk drive is inhibited when a disk is write protected
This pin is the 5V supply for the digital circuitry
This pin is the 5V supply for the analog data separator circuitry
4
Function