LPC47M182-NR SMSC [SMSC Corporation], LPC47M182-NR Datasheet - Page 91

• Manufacturer Part Number: LPC47M182-NR
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
SMSC LPC47M182
ADDRESS*
REGISTER
ADDR = 0
ADDR = 0
ADDR = 1
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 0
DLAB = 0
DLAB = 0
DLAB = 1
DLAB = 1
Table 6.32 - Register Summary for an Individual UART Channel
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write
Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
DATASHEET
91
REGISTER
SYMBOL
(Note 7)
MCR
MSR
RBR
THR
SCR
DLM
FCR
LCR
LSR
DDL
IER
IIR
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
Data Bit 0
(Note 1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
“0” if
Interrupt
Pending
FIFO
Enable
Word
Length
Select Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data Ready
(DR)
Delta Clear
to Send
(DCTS)
Bit 0
Bit 0
Bit 8
BIT 0
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
RCVR FIFO
Reset
Word
Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
Bit 9
BIT 1