SAB80C166-M-T3 SIEMENS [Siemens Semiconductor Group], SAB80C166-M-T3 Datasheet - Page 49

• Manufacturer Part Number: SAB80C166-M-T3
• Description: 16-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Figure 14
CLKOUT and READY
Notes
1)
2)
3)
4)
5)
6)
7)
Semiconductor Group
Command
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t
if READY is removed in response to the command (see Note
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
CLKOUT
RD, WR
READY
READY
Async
Sync
ALE
t
t
58
32
3)
Running cycle
t
t
t
59
30
34
2)
t
t
33
31
t
t
35
58
5)
3)
t
37
3)
1)
t
t
36
59
48
37
t
29
in order to be safely synchronized. This is guaranteed,
t
35
waitstate
READY
4)
3)
).
t
36
MUX/Tristate
t
SAB 80C166/83C166
60
4)
see 6)
6)
7)