MCZ33800R2 FREESCALE [Freescale Semiconductor, Inc], MCZ33800R2 Datasheet - Page 17

• Manufacturer Part Number: MCZ33800R2
• Description: Engine Control Integrated Circuit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Power On Reset (POR). All internal registers will be placed in
the reset state. The device has an Internal 100 kΩ resistor
pull down on the ENABLE pin.
PULSE WIDTH MODULATION (PWM)
drivers. The PWM pins provide parallel control and can be
programmed for an OR function with the SPI bit or an AND
function with the SPI bit (See
message detail). Each PWM input pin has an internal 15
pull down current source. The current sources are active
when the device is in Normal Mode.
DRAIN VOLTAGE SENSE (VDSNSX)
diagnostics of the external MOSFET:
GATE DRIVER OUTPUTS (GDX)
MOSFETS. Internal to the device is a Gate to Source resistor
designed to hold the external MOSFET in the OFF state while
the device is in POR.
INPUTS (P1, P3, P5, P7)
input control pin has an internal pull down current source.
Two outputs may be controlled in parallel using the PX pins
(See Functional Device Operation on page
VOLTAGE CALIBRATED INPUT (VCAL)
a reference voltage for analog circuits. VCAL (EXT or INT)
must be applied for the CCD1 and CCD2 constant current
controllers and Load Resistance measurement function to
Analog Integrated Circuit Device Data
Freescale Semiconductor
1. By monitoring the drain voltage of the external device,
2. The VDSNSx pins are use to determine the external
3. The VDSNSx pins provide a drain to gate clamp for
The PWM pins are control input pins for the MOSFET pre-
The VDSNSx pin has multiple functions for control and
The GDX pins are the gate drive outputs for an external
The input pins for octal serial switch outputs 1,3,5,7. Each
The Voltage calibrated input (VCAL) provides the IC with
short circuits and open circuits are detected. The filter
timer and threshold voltage are easily programmed
through SPI (see
on page 24
load resistance. Further information is provided in the
Device Operation section of this specification.
fast turn off of inductive loads and MOSFET protection.
for SPI messages).
Table 10, on page 23
Table 12, on page 25
25).
and
Table 11,
for SPI
µ
A
operate. For applications where measurements are not
critical, the VCAL pin may grounded and an internally
generated reference will be used. Using the internally
generated reference will add
parametric table.
LOAD RESISTANCE FEEDBACK (LRFDBK)
amplifier output voltage is proportional to the load resistance
for the selected channel. The channel is selected via the SPI.
DEFAULT
to a Default Mode. The DEFAULT input must be logic 0 for full
function of all output drivers. For more information on the
DEFAULT operation
page
Default Mode. The DEFAULT pin is pulled up to the VDD
supply through an active pull up current source. In Default
Mode the device operates in the following manner:
outputs and on board PWM controllers are disabled. PWMx
input control is enabled.
information and output status information. Normal operation
will resume when the DEFAULT pin transitions low again and
the device will operate as programmed prior to Default Mode.
RESISTOR EXTERNAL REFERENCE (REXT)
the load resistance of the PWM outputs. The load resistance
measurement current is inversely proportional to REXT
current. The resistor value may be changed to adjust the load
measurement current. A 24Ω resistor to ground sets the
LRFDBK output to 260mV/Ω.
EXPOSED PAD
Although the device does not use the pad for electrical
conduction, the bottom side exposed pad of the package
should be grounded.
The LRFDBK pin is an operational amplifier output. The
The DEFAULT input controls the operation of each driver
With the DEFAULT pin HIGH, the device is placed in
1. OSS outputs are disabled.
2. CCD1 and CCD2 outputs are disabled.
3. SPI ON/OFF control of GATE DRIVE (GD1 to GD6)
In the Default Mode the device retains all register
The reference current is used in the equation to calculate
The silicon die is epoxy attached to the top side of the pad.
19).
(See Functional Device Operation on
FUNCTIONAL PIN DESCRIPTION
±
10% to all tolerances in the
FUNCTIONAL DESCRIPTION
33800
17