FDC37B770 SMSC [SMSC Corporation], FDC37B770 Datasheet - Page 121

• Manufacturer Part Number: FDC37B770
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC [SMSC Corporation]

KEYBOARD ISA INTERFACE
The FDC37B77x ISA interface is functionally
compatible with the 8042 style host interface. It
consists of the D0-7 data bus; the nIOR, nIOW
and the Status register, Input Data register, and
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and
Keyboard Data Write
This is an 8 bit write only register.
written, the C/D status bit of the status register
is cleared to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output
is cleared and the OBF flag in the status register
is cleared.
AUXOBF1 must be cleared in software.
ISA ADDRESS
0x60
0x64
Data Read.
If not enabled, the KIRQ and/or
nIOW
0
1
0
1
nIOR
Table 48 - ISA I/O Address Map
1
0
1
0
When
BLOCK
KDATA
KDATA
KDCTL
KDCTL
121
Output Data register. Table 48 shows how the
interface decodes the control signals.
addition to the above signals, the host interface
includes keyboard and mouse IRQs.
Keyboard Command Write
This is an 8 bit write only register.
written, the C/D status bit of the status register
is set to one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
Keyboard Data Write (C/D=0)
Keyboard Data Read
Keyboard Command Write (C/D=1)
Keyboard Status Read
FUNCTION (NOTE 1)
When
In