PEB2447 SIEMENS [Siemens Semiconductor Group], PEB2447 Datasheet - Page 28

• Manufacturer Part Number: PEB2447
• Description: Memory Time Switch Extended Large MTSXL
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Figure 12
Internal Control Signals Mode 0 (OCSR = 0)
Note: O_SYN is a control signal for the synchronization of RD and WR access to the
This figure shows that the inputs IN0 .. IN15 are written into the data memory at the same
time whereas IN16 .. IN31 are written one O_SYN period (= 2 CLK periods) later. The
value of ICSR 0..15 shifts the sampling points and the signal “Ld Inp Buffer 1” later in
time (rightwards), the signals “Ld Inp Buffer 2” and “Wr S Memory” remain constant. In
this example with OCSR = 0 the lower Inputs IN0 .. IN15 are written into data memory
before Out15 (and Out31) is read.
With OCSR > 0 all Output Signals (Ld Outp Buffer and following) including the data
(OUT0..15) on the internal data transfer bus is shifted earlier in time (leftwards). Therefor
the data is read out of the data memory earlier.
Due to the internal timing the frame delay is depending on the programmed input / output
time slots and OCSR. The internal delay (number of time slots) can be deduced from
figure 12 and is shown in table 7.
data memory and not important for the external functionality. O_SYN frequency is
f
CLK
/ 2.
28
Operational Description
PEB 2447
03.97