PEB2080 SIEMENS [Siemens Semiconductor Group], PEB2080 Datasheet - Page 33

• Manufacturer Part Number: PEB2080
• Description: S/T Bus Interface Circuit(SBC)
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Functional Description
Q Channel
The SBC provides Q-channel support by transmitting a binary “1” in each frame in which a “1” is
received in the F
-bit position of the NT-to-TE frame. Thus interference of F
bits from one TE with
A
A
the Q bits in passive bus configurations is avoided.
LT-T Application
As in TE applications, the receive 192-kHz clock is adaptively derived from the S-interface data. The
transmit frame is shifted by two bits with respect to the receive frame.
The SBC provides a 512-kHz clock, CP, derived from the 192-kHz receive line clock with the DPLL.
If necessary, this reference clock may be used to synchronize the central system (“NT2”) clock
generator. The system timing is input over IOM interface bit and frame clocks, DCL and FSC. The
relative position of the S and IOM frame is arbitrary. Moreover, the SBC prevents a slip from
occurring if the wander between the DCL and CP clocks does not exceed a limit (The SBC enables
intermediate storage of: 3xB
, 3xB
and four D bits, for phase difference and wander absorption). ln
1
2
case a wander greater than 24 s is exceeded (cf CCITT Q.503), a warning is sent twice by the
SBC in the C/l channel (“slip”).
If the analog test loop (TL3) is closed, the 192-kHz line clock is internally derived from DCL:
therefore no slips can occur in this case.
Since only point to point configurations can be realized with the LT-T application, bus availability
indication is not required. However, the D-echo bit is still monitored and interference-free
transmission is indicated by the BUSY bit.
Semiconductor Group
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