LAN9211_0711 SMSC [SMSC Corporation], LAN9211_0711 Datasheet - Page 31

• Manufacturer Part Number: LAN9211_0711
• Description: High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
3.6.1.1
LAN9211
1DWORD
DST
0
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN
protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will
begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it
calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the RX Data FIFO with the
checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the
last byte of the Ethernet frame. The packet length field in the RX status word (refer to
will indicate that the frame size has increased by two bytes to accommodate the checksum.
Setting the RXCOE_EN bit in the
RXCOE, while the RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the
the received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
RX Checksum Calculation
The checksum is calculated 16 bits at a time. In the case of an odd sized frame, an extra byte of zero
is used to pad up to 16 bits.
Consider the following packet: DA, SA, Type, B0, B1, B2 … BN, FCS
Let [A, B] = A*256 + B;
If the packet has an even number of octets then
checksum = [B1, B0] + C0 + [B3, B2] + C1 + … + [BN, BN-1] + CN-1
Where C0, C1, ... CN-1 are the carry out results of the intermediate sums.
If the packet has an odd number of octets then
checksum = [B0, B1] + C0 + [B2, B3] + C1 + … + [0, BN] + CN-1
1
SRC
Figure 3.8 Ethernet Frame with multiple VLAN Tags and SNAP Header
state of the RXCOE_EN or RXCOE_MODE bits.
the
simultaneously.
2
{DSAP, SSAP, CTRL,
MAC_CR—MAC Control
8
1
0
0
4
OUI[23:16]}
V
I
D
8
1
0
0
5
V
I
D
L
e
n
6
S
N
A
P
0
7
S
N
A
P
1
8
COE_CR—Checksum Offload Engine Control Register
DATASHEET
Register) and vice versa. These functions cannot be enabled
{OUI[15:0], PID[15:0]}
31
Calculate Checksum
L3 Packet
Revision 1.93 (11-27-07)
Section
F
C
S
enables the
3.13.3)