LAN91C100-FD-SS SMSC [SMSC Corporation], LAN91C100-FD-SS Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
LAN91C100-FD-SS
Manufacturer Part Number
LAN91C100-FD-SS
Description
FEAST Fast Ethernet Controller with Full Duplex Capability
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN91C100-FD-SS.pdf
(67 pages)
- Current page: 47 of 67
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readback as both bits high. No other bits of the LAN91C100FD can be read or written until the EEPROM operation
completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
Note: If no EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the ENEEP pin
should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address
assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.
SMSC DS – LAN91C100FD REV. B
IOS2-0
000
001
010
011
100
101
110
XXX
FIGURE 12 - 64 X 16 SERIAL EEPROM MAP
WORD ADDRESS
0h
1h
4h
5h
8h
9h
Ch
Dh
10h
11h
14h
15h
18h
19h
20h
21h
22h
Page 47
CONFIGURATION REG.
CONFIGURATION REG.
CONFIGURATION REG.
CONFIGURATION REG.
CONFIGURATION REG.
CONFIGURATION REG.
CONFIGURATION REG.
BASE REG.
BASE REG.
BASE REG.
BASE REG.
BASE REG.
BASE REG.
BASE REG.
16 BITS
IA0-1
IA2-3
IA4-5
Rev. 01-20-06
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