USB3450-FZG SMSC [SMSC Corporation], USB3450-FZG Datasheet - Page 21

• Manufacturer Part Number: USB3450-FZG
• Description: HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
• Manufacturer: SMSC [SMSC Corporation]

Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
SMSC USB3450
6.2
6.3
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the Link and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in
The behavior of the Transmit State Machine is described below.
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This block receives serial data from the clock recovery circuits and processes it to be transferred to
the Link on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial
to parallel conversion. Upon valid assertion of the proper RX control lines, the RX Logic block will
provide bytes to the DATA bus as shown in the figures below. The behavior of the receiver is described
below.
TX Logic
RX Logic
The Link asserts TXVALID to begin a transmission.
After the Link asserts TXVALID it can assume that the transmission has started when it detects
TXREADY has been asserted.
The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID
are asserted on the rising edge of CLKOUT.
The Link must have valid packet information (PID) asserted on the DATA bus coincident with the
assertion of TXVALID.
TXREADY is sampled by the Link on the rising edge of CLKOUT.
The Link negates TXVALID to complete a packet. Once negated, the transmit logic will never
reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALD asserts again.
The USB3450 is ready to transmit another packet immediately, however the Link must conform to
the minimum inter-packet delays identified in the Hi-Speed specification.
Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3450
will sample the disconnect comparator at the 32nd bit of the 40 bit long EOP during SOF packets.
Supports FS pre-amble for FS hubs with a LS device.
Supports LS keep alive by receiving the SOF PID.
Supports Host mode resume K which ends with two low speed times of SE0 followed by 1 FS “J”.
Figure 6.3 Transmit Timing for a Data Packet
DATASHEET
21
Figure
6.3.
Revision 0.1 (05-11-05)