USB2005_07 SMSC [SMSC Corporation], USB2005_07 Datasheet - Page 9

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USB2005_07

Manufacturer Part Number
USB2005_07
Description
USB 2.0 ATA/ATAPI Controller with PD-DRM
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Chapter 4 Block Diagram
External PHY
OPTIONAL
Auto address generators
( Serial Interface Engine )
( Transciever )
RAMWR_A/B
USB2.0 PHY
RAMRD_A/B
EP0TX_BC
EP0RX_BC
EP1TX_BC
EP1RX_BC
SIE
Clocked byPhase 0 Clock
Address
Address
Address
Address
CLOCKOUT
32 bit 15MHz Data Buss
Configuration and Control
SIE Control Regs
Clock Generation
12 MHz
Osc
Address
Figure 4.1 USB2005 Block Diagram
Latch phase 0
32 Bit
512 Bytes EP2 TX/RX Buffer B
512 Bytes EP2 TX/RX Buffer A
Interrupt Controller
64 Bytes EP1RX
64 Bytes EP1TX
64 Bytes EP0RX
64 Bytes EP0TX
Latch phase 1
CPU CORE
FAST 8051
60MHz
Latch phase 2
Clocked byPhase 1 Clock
Data @ 32 bit
15MHz
1.25KB
SRAM
Future phase 3
Serial 2 wire ( Data/Strobe)
Program/Scratchpad
768 Byte
SRAM
GPIO
Debug
Interface
ATA-66
MEM/IO Bus
29pins
Clocked byPhase 2 Clock
48KB ROM
7 pins
2 pins
ATA/ATAPI
Drive
Program Memory/ IO
ROMEN
Bus

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