MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 133

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MC68HC711D3CFB2

Manufacturer Part Number
MC68HC711D3CFB2
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
B.2.3 Control Timing
B.2.4 Peripheral Port Timing
Freescale Semiconductor
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup time
Reset input pulse width
Interrupt pulse width, PW
Wait recovery startup time
Timer pulse width PW
Frequency of operation (E-clock frequency)
E-clock period
Peripheral data setup time
Peripheral data hold time
Delay time, peripheral data write
1. V
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
1. V
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
t
To guarantee external reset vector
Minimum input time can be preempted by internal reset
IRQ edge-sensitive mode
Input capture pulse accumulator input
MCU read of ports A, B, C, and D
MCU read of ports A, B, C, and D
MCU write to port A
MCU writes to ports B, C, and D
PCSU
t
otherwise noted.
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to
Resets, Interrupts, and Low-Power Modes
otherwise noted.
PWD
DD
DD
= 3.0 Vdc to 5.5 Vdc, V
= 3.0 Vd to 5.5 Vdc, V
= 1/4 t
= 1/4 t
cyc
cyc
+ 50 ns
+ 150 ns
Characteristic
TIM
(2)
(2)
IRQ
Characteristic
= t
(2)
cyc
= t
SS
SS
cyc
+ 20 ns
= 0 Vdc, T
= 0 Vdc, T
(1)
+ 20 ns
(1)
A
MC68HC711D3 Data Sheet, Rev. 2.1
A
= T
= T
for further details.
L
L
to T
to T
H
H
. All timing is shown with respect to 20% V
. All timing is shown with respect to 20% V
Symbol
t
t
PDSU
t
PWD
t
PDH
f
cyc
O
Symbol
PW
PW
PW
1000
t
Min
f
t
100
PCSU
XTAL
4 f
dc
50
WRS
t
f
cyc
RSTL
O
IRQ
TIM
O
1.0 MHz
Max
1000
1020
1020
200
350
1.0
Min
MC68L11D0 Electrical Characteristics
325
dc
dc
8
1
1.0 MHz
Max
1.0
4.0
4.0
4
Min
500
100
dc
50
DD
DD
2.0 MHz
and 70% V
and 70% V
Min
500
200
520
520
dc
dc
8
1
2.0 MHz
Max
200
225
2.0
Max
2.0
8.0
8.0
4
DD
Chapter 4
DD
, unless
, unless
MHz
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
t
t
ns
ns
ns
ns
cyc
cyc
133

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