ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 30

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

ENC28J60
4.2.2
The Read Buffer Memory (RBM) command allows the
host controller to read bytes from the integrated 8-Kbyte
transmit and receive buffer memory.
If the AUTOINC bit in the ECON2 register is set, the
ERDPT Pointer will automatically increment to point to
the next address after the last bit of each byte is read.
The next address will normally be the current address
incremented by one. However, if the last byte in the
receive buffer is read (ERDPT = ERXND), the ERDPT
Pointer will change to the beginning of the receive
buffer (ERXST). This allows the host controller to read
packets from the receive buffer in a continuous stream
without keeping track of when a wraparound is needed.
If AUTOINC is set when address 1FFFh is read and
ERXND does not point to this address, the Read
Pointer will increment and wrap around to 0000h.
The RBM command is started by pulling the CS pin low.
The RBM opcode is then sent to the ENC28J60,
followed by the 5-bit constant 1Ah. After the RBM com-
mand and constant are sent, the data stored in the
memory pointed to by ERDPT will be shifted out MSb
first on the SO pin. If the host controller continues to
provide clocks on the SCK pin, without raising CS, the
byte pointed to by ERDPT will again be shifted out MSb
first on the SO pin. In this manner, with AUTOINC
enabled, it is possible to continuously read sequential
bytes from the buffer memory without any extra SPI
command overhead. The RBM command is terminated
by raising the CS pin.
FIGURE 4-5:
DS39662B-page 28
SCK
CS
SO
SI
READ BUFFER MEMORY
COMMAND
0
0
Opcode
1
1
WRITE CONTROL REGISTER COMMAND SEQUENCE
0
2
A4
3
3
4
Address
2
5
1
6
High-Impedance State
Preliminary
0
7
D7
8
4.2.3
The Write Control Register (WCR) command allows
the host controller to write to any of the ETH, MAC and
MII Control registers in any order. The PHY registers
are written to via a special MII register interface (see
Section 3.3.2 “Writing PHY Registers” for more
information).
The WCR command is started by pulling the CS pin
low. The WCR opcode is then sent to the ENC28J60,
followed by a 5-bit address (A4 through A0). The 5-bit
address identifies any of the 32 control registers in the
current bank. After the WCR command and address
are sent, actual data that is to be written is sent, MSb
first. The data will be written to the addressed register
on the rising edge of the SCK line.
The WCR operation is terminated by raising the CS pin.
If the CS line is allowed to go high before eight bits are
loaded, the write will be aborted for that data byte.
Refer to the timing diagram in Figure 4-5 for a more
detailed illustration of the byte write sequence.
6
9
5
10
Data Byte
WRITE CONTROL REGISTER
COMMAND
4
11
3
12
2
© 2006 Microchip Technology Inc.
13
1
14
D0
15