TP3069V NSC [National Semiconductor], TP3069V Datasheet - Page 4

• Manufacturer Part Number: TP3069V
• Description: Enhanced' Serial Interface CMOS CODEC/Filter COMBO
• Manufacturer: NSC [National Semiconductor]

Functional Description
The FS
output and then the successive-approximation encoding cy-
cle begins The 8-bit code is then loaded into a buffer and
shifted out through D
coding delay will be approximately 165 s (due to the trans-
mit filter) plus 125 s (due to encoding delay) which totals
290 s Any offset voltage due to the filters or comparator is
cancelled by sign bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law and the 5th order
low pass filter corrects for the sin x x attenuation due to the
8 kHz sample hold The filter is then followed by a 2nd or-
der RC active post-filter with its output at VF
section is unity-gain but gain can be added by using the
power amplifiers Upon the occurrence of FS
the D
eight BCLK
time slot the decoding cycle begins and 10
decoder DAC output is updated The total decoder delay is
62 5 s (
E 10
R
X
s (decoder update) plus 110
input is clocked in on the falling edge of the next
frame sync pulse controls the sampling of the filter
R
frame) which gives approximately 180 s
(BCLK
X
X
) periods At the end of the decoder
at the next FS
X
(Continued)
pulse The total en-
s (filter delay) plus
R
O The receive
R
the data at
s later the
4
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer The gain of
the first power amplifier can be adjusted to boost the
peak output signal from the receive filter up to
into an unbalanced 300
anced 15 k
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads
Maximum power transfer to a 600
tion is obtained by differentially driving a balanced trans-
former with a
peak power of 15 6 dBm can be delivered to the load plus
termination
V
V
V
IN
IN
IN
e a
e
e b
0V
ENCODING FORMAT AT D
Full-Scale
Full-Scale
load The second power amplifier is internally
S
2 1 turns ratio as shown in Figure 4 A total
1
1
0
0
(Includes Even Bit Inversion)
load or
0
1
1
0
1
0
0
1
subscriber line termina-
TP3069
g
A-Law
X
0
1
1
0
4 0V into an unbal-
OUTPUT
1
0
0
1
g
0
1
1
0
3 3V peak
1
0
0
1
g
2 5V
0
1
1
0