DP8390 NSC [National Semiconductor], DP8390 Datasheet - Page 54

• Manufacturer Part Number: DP8390
• Description: NIC Network Interface Controller
• Manufacturer: NSC [National Semiconductor]

15 0 Switching Characteristics
Note 1 The NIC must synchronize to collision detect If the NIC is in the middle of serializing a byte of data the remainder of the byte will be serialized Thus the jam
pattern will start anywhere from 1 to 8 TXC cycles after COL is asserted
Note 2 The NIC always issues 32 bits of jam The jam is all 1’s data
Note 1 The RESET pulse requires that BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several
registers are affected by RESET Consult the register descriptions for details
Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low
If BSCK
If TXC
Symbol
rstw
Symbol
tcolw
tcdj
tjam
k
k
BSCK then RESET
TXC then RESET
Reset Pulse Width (Note 1)
e
e
8
8
c
c
BSCK
TXC
Collision Detect Width
Delay from Collision to First
Bit of Jam (Note 1)
Jam Period (Note 2)
Parameter
Parameter
Serial Timing Transmit (Collision)
(Continued)
Reset Timing
54
Min
8
Min
2
Max
Max
32
(Note 2)
8
BSCK Cycles or TXC Cycles
Units
TL F 8582 – 92
cycles
cycles
cycles
Units
txcyc
txcyc
txcyc
TL F 8582– 93