AT75C221-Q208 ATMEL [ATMEL Corporation], AT75C221-Q208 Datasheet - Page 13

• Manufacturer Part Number: AT75C221-Q208
• Description: Smart Internet Appliance Processor
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
ARM7TDMI Core
DSP Subsystem
Ethernet MAC
6033CS–INTAP–05/04
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor archi-
tecture is Von Neumann load/store architecture, characterized by a single data and
address bus for instructions and data. The CPU has two instruction sets: the ARM and
the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and pro-
vides maximum performance. Thumb instructions are 16-bit wide and give maximum
code density.
Instructions operate on 8-bit, 16-bit and 32-bit data types.
The CPU has seven operating modes. Each operating mode has dedicated banked reg-
isters for fast exception handling. The processor has a total of 37 32-bit registers,
including six status registers.
The AT75C221 DSP subsystem is composed of:
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The DSP subsystem is fully autonomous. The local X- and Y-RAM allows it to reach its
maximum processing rate, and a local large data RAM enables complex DSP algo-
rithms to be implemented. The large size of the loadable program RAM permits the use
of functions as complex as a low bit-rate vocoder.
During boot time, the ARM7TDMI core has the ability to maintain the OakDSPCore in
reset state and to upload DSP code. When the OakDSPCore reverts to an active state,
this code is executed.
When the OakDSPCore is running the dual-port mailbox is used as the communication
channel between the ARM7TDMI and the OakDSPCore.
A programmable codec interface is directly connected to the OakDSPCore. It allows the
connection of most industrial voice, multimedia or data codecs.
The AT75C221 features two identical Ethernet MACs with the same attributes as
follows:
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An OakDSPCore running at 60 MIPS
2K x 16 of X-RAM
2K x 16 of Y-RAM
16K x 16 of General Purpose Data RAM
32K x 16 of Loadable Program RAM
One 256 x 16 Dual-port Mailbox
One Codec Interface
Compatible with IEEE Standard 802.3
10 and 100 Mbits per Second Data Throughput Capability
Full- and Half-duplex Operation
Media Independent Interface to the Physical Layer
Register Interface to Address, Status and Control Registers
DMA Interface
Interrupt Generation to Signal Receive and Transmit Completion
28-byte Transmit and 28-byte Receive FIFOs
Automatic Pad and CRC Generation on Transmitted Frames
AT75C221 Summary
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