CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 33
CP80S54E
Manufacturer Part Number
CP80S54E
Description
EPROM/ROM-Based 8-Bit Microcontroller Series
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.CP80S54E.pdf
(47 pages)
- Current page: 33 of 47
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MOVAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
MOVIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
MOVR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
OPTION
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Move ACC to R
MOVAR R
0
ACC
None
Move data from the ACC register to register ‘R’.
1
Move Immediate to ACC
MOVIA I
0
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
Move R
MOVR R, d
0
d
R
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since
status flag Z is affected.
1
No Operation
NOP
None
No operation
None
No operation.
1
Load OPTION Register
OPTION
None
ACC
None
The content of the ACC register is loaded into the OPTION register.
1
Return from Interrupt, Set ‘GIE’ Bit
RETFIE
None
Top of Stack
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is
set to 1. This is a two-cycle instruction.
2
I
∈
≤
≤
≤
R
I
R
[0,1]
ACC
≤
dest
≤
≤
255
63
63
R
OPTION
PC
CP80S54/56
Rev0.1 Nov 30, 2005
P.33/CP80S54/S56
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