MC68CK338CPV14 FREESCALE [Freescale Semiconductor, Inc], MC68CK338CPV14 Datasheet
MC68CK338CPV14
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MC68CK338CPV14 Summary of contents
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... This document contains information on a new product. Specifications and information herein are subject to change without notice. For More Information On This Product, © MOTOROLA INC., 1996 Table 1 Ordering Information Voltage Temperature Package Order Quantity – tray 60 pc tray 300 pc tray Go to: www.freescale.com Order this document by MC68CK338TS/D MC68CK338 Order Number SPMC68CK338CPV14 MC68CK338CPV14 MC68CK338CPV14B1 ...
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Freescale Semiconductor, Inc. Section 1 Introduction 1.1 Features ......................................................................................................................................3 1.2 Block Diagram .............................................................................................................................4 1.3 Pin Assignments ..........................................................................................................................5 1.4 Address Map ...............................................................................................................................6 1.5 Intermodule Bus ..........................................................................................................................6 2 Signal Descriptions 2.1 Pin Characteristics ...................................................................................................................... 7 2.2 MCU Power Connections ............................................................................................................8 2.3 MCU ...
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Freescale Semiconductor, Inc. 1.1 Features • Modular Architecture • Low-Power Central Processing Unit (CPU32L) — Virtual memory implementation — Loop mode of instruction execution — Improved exception handling for controller applications — Table lookup and interpolate instruction — CPU-only LPSTOP ...
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Freescale Semiconductor, Inc. 1.2 Block Diagram VRTC VRTC VSSRTCOSC VSSRTCOSC EXRTC EXRTC XRTC XRTC VSSRTCOSC VSSRTCOSC CTS14A CTS14A CTS14B CTS14B CTS18A CTS18A CTS18B CTS18B CTS24A CTS24A CTS24B CTS24B CTIO[5:0] CTIO[5:0] CTD[10:4] CTD[10:4] CTD[29:26] CTD[29:26] CTM31L CTM31L RXD SS PQS7/TXD TXD ...
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Freescale Semiconductor, Inc. 1.3 Pin Assignments VDDE 1 CTD6 2 CTD7 3 CTD8 4 CTD9 5 CTD10 6 CTIO1 7 CTIO0 8 VRTC 9 MISO 10 MOSI 11 SCK 12 PCS0/SS 13 PCS1 14 PCS2 15 PCS3 16 TXD 17 ...
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Freescale Semiconductor, Inc. 1.4 Address Map Figure 3 shows a map of the MCU internal addresses. Unimplemented blocks are mapped externally M111, WHERE M IS THE STATE OF THE MODULE MAPPING (MM) BIT IN THE SIML CONFIGURATION REGISTER. ...
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Freescale Semiconductor, Inc. 2 Signal Descriptions 2.1 Pin Characteristics Table 2 shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending ...
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Freescale Semiconductor, Inc. Table 2 MCU Pin Characteristics (Continued) Pin Output Mnemonic Driver PCS0/SS Bo PCS[3:1] Bo RESET Bo RMC A R/W A RXD — SCK Bo SIZ[1:0] B TSC — TXD Bo XFC — XRTC — XTAL — NOTES: ...
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Freescale Semiconductor, Inc. 2.4 Signal Characteristics Table 5 MCU Signal Characteristics Signal Name MCU Module ADDR[23:0] AS AVEC BERR BG BGACK BKPT CPU32L BR CLKOUT CS[10:0] CSBOOT CTD[29:26] CTD[10:4] CTIO[5:0] CTM31L CTS24[B:A] CTS18[B:A] CTS14[B:A] DATA[15:0] DS DSACK[1:0] DSCLK CPU32L DSI ...
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Freescale Semiconductor, Inc. Table 5 MCU Signal Characteristics (Continued) Signal Name MCU Module RESET RMC R/W RXD SCK SIZ[1:0] SS TSC TXD XFC XRTC XTAL 2.5 Signal Function Signal Name Mnemonic Address Bus ADDR[23:0] Address Strobe AS Autovector AVEC Bus ...
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Freescale Semiconductor, Inc. Table 6 MCU Signal Function (Continued) Signal Name Mnemonic Data Strobe DS Data and Size DSACK[1:0] Acknowledge Development Serial DSI, DSO, In, Out, Clock DSCLK Function Codes FC[2:0] Freeze FREEZE Halt HALT Instruction Pipeline IFETCH, IPIPE Indicate ...
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Freescale Semiconductor, Inc. 3 Low-Power System Integration Module The low-power system integration module (SIML) consists of five functional blocks that control system startup, initialization, configuration, and the external bus. Figure 4 shows the SIML block diagram. 3.1 Overview The system ...
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Freescale Semiconductor, Inc. 1 Access Address 15 S $YFFA00 S $YFFA02 S $YFFA04 S $YFFA06 S $YFFA08 — $YFFA0A — $YFFA0C — $YFFA0E S/U $YFFA10 S/U $YFFA12 S/U $YFFA14 S $YFFA16 S/U $YFFA18 S/U $YFFA1A S/U $YFFA1C S $YFFA1E S ...
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Freescale Semiconductor, Inc. Table 7 SIML Address Map (Continued) 1 Access Address 15 S $YFFA52 S $YFFA54 S $YFFA56 S $YFFA58 S $YFFA5A S $YFFA5C S $YFFA5E S $YFFA60 S $YFFA62 S $YFFA64 S $YFFA66 S $YFFA68 S $YFFA6A S ...
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Freescale Semiconductor, Inc. EXOFF — External Clock Off 0 = The CLKOUT pin is driven by the MCU system clock The CLKOUT pin is placed in a high-impedance state. FRZSW — Freeze Software Enable 0 = When FREEZE ...
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Freescale Semiconductor, Inc. 3.3 System Clock The system clock in the SIML provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected ...
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Freescale Semiconductor, Inc. * RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768 kHZ CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. Figure 6 System Clock Oscillator Circuit ...
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Freescale Semiconductor, Inc. * MAINTAIN LOW LEAKAGE ON THE XFC NODE. Figure 7 System Clock Filter Network When the clock synthesizer is used, SYNCR determines the operating frequency of the MCU. The fol- lowing equation relates the MCU operating frequency ...
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Freescale Semiconductor, Inc. When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of SYNCR. Bits in the lower byte show the status of or control the operation of internal and ...
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Freescale Semiconductor, Inc. 3.3.5 Low-Power Operation Low-power operation is initiated by the CPU32L. To reduce power consumption selectively, the CPU32L can enter the following low-power modes: 1. The CPU32L can selectively disable a module by setting the module’s STOP bit. ...
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Freescale Semiconductor, Inc. SETUP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO 1 LEAVE IMBCLK ON IN LPSTOP? YES SET STOP BITS FOR MODULES THAT WILL NOT BE ACTIVE IN LPSTOP 2 SET STCPU = imbclk ...
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Freescale Semiconductor, Inc. 3.4 System Protection Block System protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. These functions reduce the number of external components required for complete sys- tem control. Figure ...
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Freescale Semiconductor, Inc. SWP — Software Watchdog Prescaler This bit controls the value of the software watchdog prescaler Software watchdog clock not prescaled 1 = Software watchdog clock prescaled by 512 SWT[1:0] — Software Watchdog Timing This field ...
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Freescale Semiconductor, Inc. The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy- cle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles ...
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Freescale Semiconductor, Inc. 3.4.6 Periodic Interrupt Timer The periodic interrupt timer (PIT) generates interrupts at user-programmable intervals. Timing for the PIT is provided by a programmable prescaler driven by the system clock. PICR — Periodic Interrupt Control Register 15 14 ...
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Freescale Semiconductor, Inc. PTP — Periodic Timer Prescaler Control 0 = Periodic timer clock not prescaled 1 = Periodic timer clock prescaled by 512 The reset state of PTP is the complement of the state of the MODCLK signal at ...
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Freescale Semiconductor, Inc. SIZ1 3.5.2 Function Codes The CPU32L automatically generates function code signals FC[2:0]. The function codes can be consid- ered address extensions that automatically select one of eight address spaces to which an address ...
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Freescale Semiconductor, Inc. 3.5.6 Data Strobe Data strobe (DS timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus asserted at the same time as ...
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Freescale Semiconductor, Inc. The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper- ation assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes ...
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Freescale Semiconductor, Inc. Current 1 Transfer Case Cycle 1 Byte to 8-bit port (even) 2 Byte to 8-bit port (odd) 3 Byte to 16-bit port (even) 4 Byte to 16-bit port (odd) 5 Word to 8-bit port 6 Word to ...
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Freescale Semiconductor, Inc. When a memory access occurs, chip-select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. If all parameters match, ...
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Freescale Semiconductor, Inc. Table 18 Chip-Select Pin Functions Assignment Register CSPAR0 CSPAR1 Table 19 shows pin assignment field encoding. Pins that have no discrete output function do not use the %00 encoding. Table 19 Pin Assignment Encodings CSPAR0 — Chip-Select ...
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Freescale Semiconductor, Inc. Table 20 CSPAR0 Pin Assignments CSPAR0 Field Chip-Select Signal CS5PA[1:0] CS4PA[1:0] CS3PA[1:0] CS2PA[1:0] CS1PA[1:0] CS0PA[1:0] CSBTPA[1:0] CSPAR1 — Chip-Select Pin Assignment Register RESET ...
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Freescale Semiconductor, Inc. Table 22 CSPAR1 Pin Assignments CSPAR1 Field Chip-Select Signal CS10PA[1:0] CS9PA[1:0] CS8PA[1:0] CS7PA[1:0] CS6PA[1:0] Port size determines the way in which bus transfers to external addresses are allocated. Port size of eight bits or sixteen bits can ...
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Freescale Semiconductor, Inc. CSBAR[0:10] — Chip-Select Base Address Registers ADDR ADDR ADDR ADDR ADDR ADDR RESET ADDR[23:11] — Base Address Field This field sets the ...
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Freescale Semiconductor, Inc. CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera- tion from peripheral memory devices. The following bit descriptions apply to both CSORBT and CSOR[0:10] option registers. MODE — Asynchronous/Synchronous Mode 0 = ...
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Freescale Semiconductor, Inc. DSACK[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SPACE[1:0] — Address Space Use this option field to select an address space for the chip-select logic. The CPU32L normally ...
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Freescale Semiconductor, Inc. Table 28 Interrupt Priority Level Field Encoding This field only affects the response of chip-selects and does not affect interrupt recognition by the CPU. Any level means that chip-select is asserted regardless of the level of the ...
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Freescale Semiconductor, Inc. PORTE0, PORTE1— Port E Data Register NOT USED RESET: A write to the port E data register is stored in the internal data latch and, if any port E pin is configured ...
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Freescale Semiconductor, Inc. PEPAR Bit PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 PORTF0, PORTF1 — Port F Data Register NOT USED RESET: The write to the port F data register is stored in the ...
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Freescale Semiconductor, Inc. PFPAR Field PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0 Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the register is set to $FF, which ...
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Freescale Semiconductor, Inc. Mode Select Pin DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT Data lines have weak internal pull-up drivers. External bus loading can overcome the weak internal pull- up drivers on data bus ...
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Freescale Semiconductor, Inc. Pin(s) While RESET CS10/ADDR23/ECLK CS[9:6]/ADDR[22:19]/PC[6:3] ADDR[18:0] AS/PE5 AVEC/PE2 BERR CS1/BG CS2/BGACK CS0/BR CLKOUT CSBOOT DATA[15:0] Mode select DS/PE4 DSACK0/PE0 DSACK1/PE1 CS[5:3]/FC[2:0]/PC[2:0] HALT IRQ[7:1]/PF[7:1] MODCLK/PF0 Mode Select R/W RESET RMC/PE3 SIZ[1:0]/PE[7:6] TSC Mode select 3.8.3 Functions of Pins ...
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Freescale Semiconductor, Inc internal source asserts the reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues ...
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Freescale Semiconductor, Inc. The CPU32L provides seven levels of interrupt priority (1–7), seven automatic interrupt vectors, and 200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the in- terrupt priority (IP) field in status ...
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Freescale Semiconductor, Inc. Arbitration is performed by means of serial contention between values stored in individual module inter- rupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the SIML, has an IARB field in its ...
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Freescale Semiconductor, Inc. A. The CPU finishes higher priority exception processing or reaches an instruction boundary. B. The processor state is stacked. The S bit in the status register is set, establishing supervisor access level, and bits T1 and T0 ...
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Freescale Semiconductor, Inc. 4 Low-Power Central Processor Unit Based on the powerful MC68020, the CPU32L processing module provides enhanced system perfor- mance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview The CPU32L is fully ...
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Freescale Semiconductor, Inc Figure 12 User Programming Model MC68CK338 For More Information On This Product, MC68CK338TS (SSP ...
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Freescale Semiconductor, Inc Figure 13 Supervisor Programming Model Supplement 4.3 Status Register The status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. ...
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Freescale Semiconductor, Inc. 4.4 Data Types Six basic data types are supported: • Bits • Packed Binary Coded Decimal Digits • Byte Integers (8 bits) • Word Integers (16 bits) • Long Word Integers (32 bits) • Quad Word Integers ...
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Freescale Semiconductor, Inc. Table 33 Instruction Set Summary Instruction Syntax Dn, Dn ABCD (An), (An) Dn, <ea> ADD <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ # <data>, <ea> Dn, Dn ADDX (An), (An) <ea>, Dn AND Dn, <ea> ...
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Freescale Semiconductor, Inc. Table 33 Instruction Set Summary (Continued) Instruction Syntax CMPM (An) , (An) CMP2 <ea>, Rn DBcc Dn, label DIVS/DIVU <ea>, Dn <ea> DIVSL/DIVUL <ea>, Dq <ea> EOR Dn, <ea> EORI # ...
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Freescale Semiconductor, Inc. Table 33 Instruction Set Summary (Continued) Instruction Syntax list, <ea> MOVEM <ea>, list Dn, (d16, An) MOVEP (d16, An), Dn MOVEQ #<data>, Dn Rn, <ea> 1 MOVES <ea>, Rn <ea>, Dn MULS/MULU <ea>, Dl <ea> ...
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Freescale Semiconductor, Inc. Table 33 Instruction Set Summary (Continued) Instruction Syntax Scc <ea> 1 #<data> STOP <ea>, Dn SUB Dn, <ea> SUBA <ea>, An SUBI #<data>, <ea> SUBQ #<data>, <ea> Dn, Dn SUBX (An), (An) SWAP Dn TAS <ea> <ea>, ...
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Freescale Semiconductor, Inc. 4.7 Background Debugging Mode The background debugger on the CPU32L is implemented in CPU microcode. The background debug- ging commands are summarized in Table 34. Table 34 Background Debugging Mode Commands Command Read D/A Register RDREG/RAREG Write ...
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Freescale Semiconductor, Inc. 5 Queued Serial Module The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). Figure 14 shows the QSM block diagram. INTERFACE 5.1 Overview The QSPI provides easy peripheral ...
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Freescale Semiconductor, Inc. 5.2 Address Map The “Access” column in the QSM address map in Table 35 indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege ...
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Freescale Semiconductor, Inc. 5.3 Pin Function Table summary of the functions of the QSM pins when they are not configured for general-pur- pose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an ...
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Freescale Semiconductor, Inc. STOP — Stop Enable 0 = Normal QSM clock operation 1 = QSM clock operation stopped STOP places the QSM in a low-power state by disabling the system clock in most parts of the module. The QSMCR ...
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Freescale Semiconductor, Inc. ILSCI — Interrupt Level of SCI ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts disabled (highest priority). If ILQSPI and ILSCI are the same nonzero value, ...
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Freescale Semiconductor, Inc. PQSPAR — PORT QS Pin Assignment Register DDRQS — PORT QS Data Direction Register PQSPA6 PQSPA5 PQSPA4 PQSPA3 RESET Clearing a bit in the PQSPAR assigns ...
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Freescale Semiconductor, Inc. Table 38 Effect of DDRQS on QSM Pin Function QSM Pin Mode MISO Master Slave MOSI Master Slave 1 SCK Master Slave PCS0/SS Master Slave PCS[3:1] Master Slave 2 TXD Transmit RXD Receive NOTES: 1. PQS2 is ...
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Freescale Semiconductor, Inc. 5.5 QSPI Submodule The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products. Figure 15 shows a block ...
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Freescale Semiconductor, Inc. 5.5.1 QSPI Pins Seven pins are associated with the QSPI. When not needed for a QSPI function, they can be configured as general-purpose I/O pins. The PCS0/SS pin can function as a peripheral chip select output, slave ...
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Freescale Semiconductor, Inc. SPCR0 — QSPI Control Register MSTR WOMQ BITS[3:0] RESET SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write ...
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Freescale Semiconductor, Inc. CPOL — Clock Polarity 0 = The inactive state value of SCK is logic level zero The inactive state value of SCK is logic level one. CPOL is used to determine the inactive state value ...
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Freescale Semiconductor, Inc. DTL[7:0] — Length of Delay after Transfer When the DT bit in command RAM is set, this field determines the length of delay after serial transfer. The following equation is used to calculate the delay: Delay after ...
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Freescale Semiconductor, Inc. SPCR3 — QSPI Control Register LOOPQ RESET SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM ...
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Freescale Semiconductor, Inc. CPTQP[3:0] — Completed Queue Pointer CPTQP[3:0] points to the last command executed updated when the current command is complete. When the first command in a queue is executing, CPTQP[3:0] contains either the reset value ($0) ...
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Freescale Semiconductor, Inc. Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI cannot modify information in the transmit data RAM. The QSPI copies the information to its data serial- izer for transmission. ...
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Freescale Semiconductor, Inc. 5.5.4 Operating Modes The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU through ...
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Freescale Semiconductor, Inc. SCCR0 — SCI Control Register RESET SCCR0 contains a baud rate selection parameter. Baud rate must be set before the SCI is enabled. ...
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Freescale Semiconductor, Inc. SCCR1 — SCI Control Register LOOPS WOMS ILT PT RESET SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any ...
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Freescale Semiconductor, Inc. M — Mode Select 0 = SCI frame: one start bit, eight data bits, one stop bit (10 bits total SCI frame: one start bit, nine data bits, one stop bit (11 bits total) WAKE ...
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Freescale Semiconductor, Inc. SCSR contains flags that show SCI operational conditions. These flags can be cleared either by hard- ware special acknowledgment sequence. The sequence consists of SCSR read with flags set, followed by SCDR read (write ...
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Freescale Semiconductor, Inc. NF — Noise Error Flag noise detected on the received data 1 = Noise occurred on the received data NF is set when the SCI receiver detects noise on a valid start bit, on ...
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Freescale Semiconductor, Inc. 6 Configurable Timer Module 6 The configurable timer module 6 (CTM6) belongs to a family of timer modules for the Motorola Modular Microcontroller Family. The timer architecture is modular relative to the number of time bases (counter ...
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Freescale Semiconductor, Inc. EXTERNAL CLOCK LOAD MODULUS COUNTER SUBMODULE (MCSM30) LOAD CTM31L MODULUS COUNTER SUBMODULE (MCSM31) EXTERNAL CLOCK LOAD MODULUS COUNTER SUBMODULE (MCSM2) FREE-RUNNING SUBMODULE (FCSM3) SRAM SUBMODULE (RAMSM32) SRAM SUBMODULE (RAMSM36) GLOBAL TIME BASE BUS A GLOBAL TIME BASE ...
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Freescale Semiconductor, Inc. 6.2 Address Map The CTM6 address map occupies 512 bytes. All CTM6 registers are addressable in supervisor space only. Table 45 shows the CTM6 register. Address 15 1 $YFF400 $YFF402 $YFF404 $YFF406 $YFF408 $YFF40A $YFF40C –$YFF40E $YFF410 ...
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Freescale Semiconductor, Inc. Table 45 CTM6 Address Map (Continued) Address 15 $YFF450 $YFF452 $YFF454 $YFF456 – $YFF45E $YFF460 $YFF462 $YFF464 $YFF466 $YFF468 – $YFF46E $YFF470 $YFF472 $YFF474 $YFF476 $YFF478 – $YFF47E $YFF480 $YFF482 $YFF484 $YFF486 $YFF488 $YFF48A – $YFF48E $YFF490 ...
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Freescale Semiconductor, Inc. Table 45 CTM6 Address Map (Continued) Address 15 $YFF4E8 $YFF4EA $YFF4EC $YFF4EE $YFF4F0 $YFF4F2 $YFF4F4 $YFF4F6 $YFF4F8 $YFF4FA $YFF4FC $YFF4FE $YFF500 – $YFF51E $YFF520 – $YFF53E $YFF540 – $YFF5FE NOTES M111, where M is ...
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Freescale Semiconductor, Inc. SUBMODULE M SUBMODULE M+1 SUBMODULE N Figure 18 Time Base Bus Configuration As shown in Figure 18, each CTM submodule can access one of two global time base buses. TBB1 and TBB4 are collectively referred to as ...
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Freescale Semiconductor, Inc. The time base buses are precharge/discharge type buses with wired-OR capability, so that no hardware damage occurs when several counters are driving the same bus at the same time. 6.4 Bus Interface Unit Submodule (BIUSM) The BIUSM ...
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Freescale Semiconductor, Inc. IARB[2:0] — Interrupt Arbitration Field This bit field and the IARB3 bit within each submodule provide 15 different interrupt arbitration numbers that can be used to arbitrate between interrupt requests occurring on the IMB with the same ...
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Freescale Semiconductor, Inc. FIRST CPSM PRESCALER f sys 6.5.1 CPSM Registers The CPSM contains a control register and a test register. All unused bits and reserved address loca- tions return zero when read by the software. Writing ...
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Freescale Semiconductor, Inc. Table 49 Prescaler Division Ratio Select Field Prescaler Control Register Bits PRUN DIV23 PSEL1 PSEL0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 ...
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Freescale Semiconductor, Inc. In order to count, the FCSM requires the CPSM clock signals to be present. On coming out of reset, the FCSM does not count internal or external events until the prescaler in the CPSM starts running (when ...
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Freescale Semiconductor, Inc. IL[2:0] — Interrupt Level Setting IL[2: non-zero value causes the FCSM to request an interrupt of the selected level when the COF bit sets. If IL[2:0] = %000, no interrupt will be requested when COF ...
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Freescale Semiconductor, Inc. FCSM3CNT — FCSM Counter Register RESET The FCSM counter register is a read/write register. A read returns the current value of the counter. A write loads the ...
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Freescale Semiconductor, Inc. 6.8.1 MCSM Registers The MCSM contains a status/interrupt/control register, a counter, and a modulus latch. All unused bits and reserved address locations return zero when read. Writing to unused bits and reserved address locations has no effect. ...
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Freescale Semiconductor, Inc. IN2 — Clock Input Pin Status This read-only status bit reflects the logic state of the clock input pin. Writing to this bit has no effect, nor does reset. The clock input of MCSM2 is internally connected ...
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Freescale Semiconductor, Inc. The clock input of MCSM2 is internally connected to I/O pin CTD27 for DASM27 and will read the state of that pin. The clock inputs of MCSM30 and MCSM31 are internally connected to I/O pin CTD5 for ...
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Freescale Semiconductor, Inc. All of the functions associated with one pin are called a SASM channel. The SASM can perform a single timing action (input capture or output compare) before software inter- vention is required. Each channel includes a 16-bit ...
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Freescale Semiconductor, Inc. SIC12B, SIC14B — SASM Status/Interrupt/Control Register B SIC18B, SIC24B — SASM Status/Interrupt/Control Register FLAG RESET SICA and SICB contain the control and ...
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Freescale Semiconductor, Inc. This bit field affects both SASM channels, not just channel A. IEN — Interrupt Enable This control bit enables interrupts when FLAG is set and the IL[2:0] field is non-zero Interrupts disabled 1 = Interrupts ...
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Freescale Semiconductor, Inc. Table 57 SASM Operating Mode Select MODE1 S12DATA, S14DATA — SASM Data Register A S18DATA, S24DATA — SASM Data Register RESET S12DATB, ...
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Freescale Semiconductor, Inc. Table 58 DASM Modes of Operation Mode DIS Disabled — I/O pin is placed in a high impedance state IPWM Input pulse width measurement — Capture on leading and the trailing edges of an input pulse IPM ...
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Freescale Semiconductor, Inc. BUS BSL SELECT 16-BIT COMPARATOR A 16-BIT REGISTER A 16-BIT REGISTER B1 REGISTER B 16-BIT REGISTER B2 16-BIT COMPARATOR B MODE3 MODE2 MODE1 MODE0 CONTROL REGISTER BITS 6.10.1 DASM Registers The DASM contains one status/interrupt/control register and ...
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Freescale Semiconductor, Inc. FLAG — Event Flag This status bit indicates whether or not an input capture or output compare event has occurred. If the IL[2:0] field is non-zero, an interrupt request is generated when FLAG is set ...
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Freescale Semiconductor, Inc. IN — Input Pin Status In the DIS, IPWM, IPM and IC modes, this read-only status bit reflects the logic level on the input pin. In the OCB, OCAB and OPWM modes, reading this bit returns the ...
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Freescale Semiconductor, Inc. To avoid spurious interrupts, DASM interrupts should be disabled before changing the operating mode. Table 62 DASM Mode Select Field Bits of MODE[3:0] Resolution 0000 — 0001 16 0010 16 0011 16 0100 16 0101 16 011X ...
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Freescale Semiconductor, Inc. Mode DIS DASMA can be accessed to prepare a value for a subsequent mode selection IPWM DASMA contains the captured value corresponding to the trailing edge of the measured pulse DASMA contains the captured value corresponding to ...
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Freescale Semiconductor, Inc. Mode DASMB can be accessed to prepare a value for a subsequent mode selection. In this mode, register DIS B1 is accessed in order to prepare a value for the OPWM mode. Unused register B2 is hidden ...
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Freescale Semiconductor, Inc. 32-BIT FREE-RUNNING 32-BIT FREE-RUNNING COUNTER BUFFER STATUS, INTERRUPT, AND CONTROL REGISTER BITS FLAG (1 Hz) NOTES: 1. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768 kHz CRYSTAL. SPECIFIC COMPONENTS MUST BE ...
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Freescale Semiconductor, Inc. TICKF is only cleared if the 32-bit free-running counter does not increment be- tween reading RTC16SIC with TICKF set to one and then writing TICKF to zero. IL[2:0] — Interrupt Level Field Setting IL[2: non-zero ...
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Freescale Semiconductor, Inc. R16FRCH — RTCSM Free-Running Counter High Register RESET R16FRCH contains the synchronized high word value of the 32-bit free-running counter or the value to be loaded into ...
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Freescale Semiconductor, Inc. 6.12.1 PIOSM Register The PIOSM control register is composed of two 8-bit registers. The upper eight bits contain the data register and the lower eight bits contain the data direction register. Each PIOSM pin may be pro- ...
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Freescale Semiconductor, Inc. RTCSM registers are write protected in standby mode to prevent loss of data in runaway situations. For the same reason, the RAMSMs are also write protected in standby mode. If the standby mode function is not required ...
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Freescale Semiconductor, Inc. Table 66 CTM6 Interrupt Priority and Vector/Pin Allocation Submodule Submodule Base Name Address BIUSM $YFF400 CPSM $YFF408 MCSM2 $YFF410 FCSM3 $YFF418 DASM4 $YFF420 DASM5 $YFF428 DASM6 $YFF430 DASM7 $YFF438 DASM8 $YFF440 DASM9 $YFF448 DASM10 $YFF450 SASM12 $YFF460 ...
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Freescale Semiconductor, Inc. 7 Electrical Characteristics This section contains electrical specification tables and reference timing diagrams. Num Rating Supply Voltage Input Voltage Instantaneous Maximum Current 3 Single pin limit (applies to ...
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Freescale Semiconductor, Inc. Num Characteristic Thermal Resistance 1 Plastic 144-Pin Surface Mount The average chip-junction temperature (T where Ambient Temperature Package Thermal Resistance, Junction-to-Ambient, C INT INT ...
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Freescale Semiconductor, Inc. (V and V DD DDSYN Num Characteristic 1 PLL Reference Frequency Range 2 System Frequency 2 On-Chip PLL System Frequency Range External Clock Operation PLL Lock Time 7 4 VCO Frequency ...
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Freescale Semiconductor, Inc. (V and V DD DDSYN Num Characteristic 1 Input High Voltage 2 Input Low Voltage 1 3 Input Hysteresis 2 Input Leakage Current Input-only pins High Impedance (Off-State) ...
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Freescale Semiconductor, Inc. Table 70 DC Characteristics (Continued) (V and V DD DDSYN Num Characteristic 2, 10 Input Capacitance 17 All input-only pins All input/output pins 2 Load Capacitance Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE/DSO 18 Group 2 I/O ...
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Freescale Semiconductor, Inc. (V and V DD DDSYN Num Characteristic F1 Frequency of Operation 1 Clock Period 1A ECLK Period 2 1B External Clock Input Period 2, 3 Clock Pulse Width 2A, 3A ECLK Pulse Width 2B, 3B External Clock ...
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Freescale Semiconductor, Inc. (V and V DD DDSYN Num Characteristic 27 Data In Valid to Clock Low (Data Setup) 27A Late BERR, HALT Asserted to Clock Low (Setup Time) 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated 29 ...
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Freescale Semiconductor, Inc. NOTES: 1. All AC timing is shown with respect to 20 When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable t period is ...
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Freescale Semiconductor, Inc. 4 CLKOUT NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V Figure 26 CLKOUT Output Timing Diagram 4B EXTAL NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% V PULSE WIDTH SHOWN WITH RESPECT TO 50% ...
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Freescale Semiconductor, Inc. CLKOUT ADDR[23:20] FC[2:0] SIZ[1: R/W DSACK0 DSACK1 DATA[15:0] BERR HALT IFETCH BKPT ASYNCHRONOUS INPUTS Figure 29 Read Cycle Timing Diagram MOTOROLA For More Information On This Product, 120 ...
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Freescale Semiconductor, Inc. S0 CLKOUT 6 ADDR[23:20] FC[2:0] SIZ[1: R/W DSACK0 DSACK1 DATA[15:0] BERR HALT BKPT Figure 30 Write Cycle Timing Diagram MC68CK338 For More Information On This Product, MC68CK338TS ...
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Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[2:0] SIZ[1: R/W DATA[15:0] BKPT Figure 31 Fast Termination Read Cycle Timing Diagram MOTOROLA For More Information On This Product, 122 14B ...
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Freescale Semiconductor, Inc. CLKOUT ADDR[23:0] FC[2:0] SIZ[1: R/W DATA[15:0] BKPT Figure 32 Fast Termination Write Cycle Timing Diagram MC68CK338 For More Information On This Product, MC68CK338TS 14B ...
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Freescale Semiconductor, Inc CLKOUT ADDR[23:0] DATA[15: R/W DSACK0 DSACK1 BR BG BGACK Figure 33 Bus Arbitration Timing Diagram — Active Bus Case MOTOROLA For More Information On This Product, 124 S98 A5 ...
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Freescale Semiconductor, Inc. A0 CLKOUT ADDR[23:0] DATA[15:0] AS 47A BGACK Figure 34 Bus Arbitration Timing Diagram — Idle Bus Case MC68CK338 For More Information On This Product, MC68CK338TS 47A to: ...
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Freescale Semiconductor, Inc. CLKOUT 6 ADDR[23: DATA[15:0] BKPT NOTE: Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion. Figure 35 Show Cycle ...
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Freescale Semiconductor, Inc CLKOUT 6 ADDR[23:0] FC[2:0] SIZ[1: R/W DATA[15:0] Figure 36 Chip Select Timing Diagram 77 RESET DATA[15:0], MODCLK, BKPT Figure 37 Reset and Mode Select Timing Diagram MC68CK338 ...
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Freescale Semiconductor, Inc. Table 72 Background Debugging Mode Timing (V and V DD DDSYN Num Characteristic B0 DSI Input Setup Time B1 DSI Input Hold Time B2 DSCLK Setup Time B3 DSCLK Hold Time B4 DSO Delay Time B5 DSCLK ...
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Freescale Semiconductor, Inc. CLKOUT FREEZE IFETCH/DSI Figure 39 Background Debugging Mode Timing Diagram — (V and V DD DDSYN Num Characteristic 1A ECLK Period 2A, 3A ECLK Pulse Width E1 ECLK Low to Address Valid E2 ECLK Low to Address ...
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Freescale Semiconductor, Inc. CLKOUT 2A ECLK R/W E1 ADDR[23: E15 DATA[15:0] E11 DATA[15:0] MOTOROLA For More Information On This Product, 130 3A 1A E14 E13 WRITE Figure 40 ECLK Timing Diagram Go to: www.freescale.com ...
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Freescale Semiconductor, Inc. (V and V = 2.7 to 3.6 Vdc DDSYN Num Function Operating Frequency 1 Master Slave Cycle Time 2 Master Slave Enable Lead Time 3 Master Slave Enable Lag Time 4 Master Slave Clock (SCK) ...
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Freescale Semiconductor, Inc. PCS[3:0] OUTPUT SCK CPOL=0 OUTPUT SCK CPOL=1 OUTPUT 6 7 MISO MSB IN INPUT MOSI MSB OUT PD OUTPUT 13 Figure 41 QSPI Timing — Master, CPHA = 0 PCS[3:0] OUTPUT SCK CPOL=0 OUTPUT SCK CPOL=1 OUTPUT ...
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Freescale Semiconductor, Inc. SS INPUT SCK CPOL=0 INPUT SCK CPOL=1 INPUT 8 MISO MSB OUT OUTPUT 6 MOSI MSB IN INPUT Figure 43 QSPI Timing — Slave, CPHA = 0 SS INPUT SCK CPOL=0 INPUT 2 SCK CPOL=1 INPUT 8 ...