MPC8536EBVTAVL FREESCALE [Freescale Semiconductor, Inc], MPC8536EBVTAVL Datasheet
MPC8536EBVTAVL
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MPC8536EBVTAVL Summary of contents
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Freescale Semiconductor Data Sheet: Product Preview MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications • High-performance, 32-bit e500 core, scaling up to 1.5 GHz, that implements the Power Architecture™ technology – 36-bit physical addressing – Double-precision embedded floating point APU using ...
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Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 1.1 Pin Map . . . . . . . . . . ...
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Figure 1 shows the major functional units within the MPC8536E. MPC8536E Performance Monitor Enhanced Local Bus Timers USB USB USB SD Host/ Host/ Host/ MMC Device Device Device ULPI ULPI ULPI 1 Pin Assignments and Reset States The naming convention ...
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Pin Map 1.1 Pin Map Figure 2 provides a bottom view of the pin map of the MPC8536E MDQ MDQ MDQ MDQ MDQS GND [5] [32] [46] [47] [34] ...
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MDQ MDQS [32] [5] MDQ MDQ MDM MDQS 2 [44] [40] [5] [5] MDQ MDQ MCS 3 GND [45] [41] [0] MBA MCS MWE [0] [2] MA MBA 5 MRAS ...
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Pin Map TSEC3_ AVDD_ MDQ TSEC3_ RXD [59] SRDS2 RX_CLK [3] TSEC3_ AGND_ MDQ TSEC3_ RXD [63] SRDS2 RX_DV [1] SD2_ TSEC3_ TSEC3_ GV DD PLL_ RXD RXD TPA [2] [0] Rvsd TSEC3_ TV DD GND ...
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MDQ MDQ GND [26] [31] MDQ MDQS MDQ MDQ 16 [30] [3] [19] [23] MDM MDQS GND [3] [3] MDQ MDQ MDM MDQS 18 [25] [24] [2] [2] MDQ MDQ MDQ 19 NC [29] ...
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Pin Map SENSE- VDD_ GND GND VDD_ CORE CORE VDD_ VDD_ SENSE- GND VSS CORE CORE VDD_ VDD_ GND GND PLAT PLAT VDD_ VDD_ GND GND PLAT PLAT TRIG_ VDD_ OUT/READY GND GND PLAT /QUIESCE SD1_TX SD1_TX XV DD XGND ...
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Table 1 provides the pin-out listing for the MPC8536E 783 FC-PBGA package. Signal PCI1_AD[31:0] Muxed Address / data PCI1_C_BE[3:0] Command/Byte Enable PCI1_PAR Parity PCI1_FRAME Frame PCI1_TRDY Target Ready PCI1_IRDY Initiator Ready PCI1_STOP Stop PCI1_DEVSEL Device Select PCI1_IDSEL Init Device Select ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal MDQ[0:63] Data MECC[0:7] Error Correcting Code MAPAR_ERR Address Parity Error MAPAR_OUT Address Parity Out MDM[0:8] Data Mask MDQS[0:8] Data Strobe MDQS[0:8] Data Strobe MA[0:15] Address MBA[0:2] Bank Select MWE Write Enable ...
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Table 1. MPC8536E Pinout Listing (continued) Signal LAD[0:31] Muxed data / address LDP[0:3] Data parity LA[27] Burst address LA[28:31] Port address LCS[0:4] Chip selects LCS5/DMA_DREQ2 Chips selects / DMA Request H16 LCS6/DMA_DACK2 Chips selects / DMA Ack LCS7/DMA_DDONE2 Chips selects ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal DMA_DREQ[0:1] DMA Request /GPIO[14:15] DMA_DDONE[0:1] DMA Done /GPIO[12:13] DMA_DREQ[2]/LCS[5] Chips selects / DMA Request H16 DMA_DACK[2]/LCS[6] Chips selects / DMA Ack DMA_DDONE[2]/LCS[7] Chips selects / DMA Done DMA_DREQ[3]/IRQ[9] External interrupt/DMA request ...
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Table 1. MPC8536E Pinout Listing (continued) Signal USB3_DIR USB3 Data Direction USB3_STP USB3 Stop Reserved — USB3_CLK USB3 bus clock MCP Machine check processor UDE Unconditional debug event IRQ[0:8] External interrupts IRQ[9]/DMA_DREQ[3] External interrupt/DMA request IRQ[10]/DMA_DACK[3] External interrupt/DMA Ack IRQ[11]/DMA_DDONE[3] ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal TSEC3_TXD[7:0] Transmit data TSEC3_TX_EN Transmit Enable TSEC3_TX_ER Transmit Error TSEC3_TX_CLK Transmit clock In TSEC3_GTX_CLK Transmit clock Out TSEC3_CRS Carrier sense TSEC3_COL Collision detect TSEC3_RXD[7:0] Receive data TSEC3_RX_DV Receive data valid TSEC3_RX_ER ...
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Table 1. MPC8536E Pinout Listing (continued) Signal UART_CTS[0:1] Clear to send UART_RTS[0:1] Ready to send UART_SIN[0:1] Receive data UART_SOUT[0:1] Transmit data IIC1_SCL Serial clock IIC1_SDA Serial data IIC2_SCL Serial clock IIC2_SDA Serial data SD1_TX[7:0] Transmit Data (+) SD1_TX[7:0] Transmit Data(-) ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal Reserved GPIO[0:1]/PCI1_REQ[3:4] GPIO/PCI request GPIO[2:3]/PCI1_GNT[3:4] GPIO/PCI grant GPIO[4]/SDHC_CD GPIO/SDHC card detection GPIO[5]/SDHC_WP GPIO/SDHC write protection AG10 GPIO[6]/USB1_PCTL0 GPIO/USB1 PCTL0 GPIO[7]/USB1_PCTL1 GPIO/USB1 PCTL1 GPIO[8]/USB2_PCTL0 GPIO/USB2 PCTL0 GPIO[9]/USB2_PCTL1 GPIO/USB2 PCTL1 GPIO[10:11] GPIO/DMA Ack ...
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Table 1. MPC8536E Pinout Listing (continued) Signal TCK Test clock TDI Test data in TDO Test data out TMS Test mode select TRST Test reset L1_TSTCLK L1 test clock L2_TSTCLK L2 test clock LSSD_MODE LSSD Mode TEST_SEL Test select ASLEEP ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal SVDD SerDes 1 core logic supply XVDD SerDes 1 transceiver supply S2VDD SerDes 2 core logic supply X2VDD SerDes 2 transceiver supply VDD_CORE Core, L2 logic supply VDD_PLAT Platform logic supply ...
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Table 1. MPC8536E Pinout Listing (continued) Signal XGND SerDes 1Transceiver pad GND (xpadvss) SGND SerDes 1 Transceiver core logic GND (xcorevss) X2GND SerDes 2 Transceiver pad GND (xpadvss) S2GND SerDes 2 Transceiver core logic GND (xcorevss) AGND_SRDS SerDes 1 PLL ...
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Pin Map Table 1. MPC8536E Pinout Listing (continued) Signal Notes: 1. All multiplexed signals may be listed only once and may not re-occur. 2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin This ...
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Table 1. MPC8536E Pinout Listing (continued) Signal 25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI ...
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Overall DC Electrical Characteristics Table 2. Absolute Maximum Ratings Characteristic DDR SDRAM DDR2 SDRAM Interface Controller I/O DDR3 SDRAM Interface supply voltage Three-speed Ethernet I/O, MII management voltage PCI, DUART, system control and power management, I eSDHC, eSPI and JTAG ...
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Table 3. Recommended Operating Conditions (continued) Characteristic Pad power supply for SerDes transceivers and PCI Express DDR SDRAM DDR2 SDRAM Interface Controller I/O supply DDR3 SDRAM Interface voltage Three-speed Ethernet I/O voltage PCI, DUART, system control and power management, I ...
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Overall DC Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8536E. B/G/L/OV DD B/G/L/OV B/G/L/ GND – 0 GND – 0.7 V Note refers to the ...
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Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Driver Type Local bus interface utilities signals PCI signals DDR2 signal DDR3 signal TSEC signals DUART, system control, JTAG ...
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Power Characteristics 2.3 Power Characteristics The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Table 5. Core CCB DDR Frequen Frequen Frequen Power Mode cy ...
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Table 5. MPC8536E Power Dissipation (continued) Core CCB DDR Frequen Frequen Frequen Power Mode cy cy (MHz) (MHz) (MHz) Maximum (A) 1250 500 Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) 1333 533 ...
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Power Characteristics Table 5. MPC8536E Power Dissipation (continued) Core CCB DDR Frequen Frequen Frequen Power Mode cy cy (MHz) (MHz) (MHz) Maximum (A) 1500 500 Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Notes: 1. ...
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Input Clocks 2.4.1 System Clock Timing Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8536E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK ...
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Input Clocks 2.4.4 eTSEC Gigabit Reference Clock Timing Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8536E. Table 8. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK rise and fall time ...
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Platform to FIFO Restrictions Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency” in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs ...
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DDR2 and DDR3 SDRAM 2.6 DDR2 and DDR3 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8536E. Note that DDR2 SDRAM is GV (type) = 1.8 V and DDR3 SDRAM is ...
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Table 14 provides the DDR capacitance when GV Table 14. DDR2 SDRAM Capacitance for GV Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled. GV (peak-to-peak This ...
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DDR2 and DDR3 SDRAM Table 17. DDR3 SDRAM Input AC Timing Specifications for 1.5-V Interface At recommended operating conditions with GV Parameter AC input low voltage AC input high voltage Table 18. DDR2 and DDR3 SDRAM Interface Input AC Timing ...
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DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications Table 19 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface. Table 19. DDR SDRAM Output AC Timing Specifications At recommended operating conditions with GV Parameter ...
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DDR2 and DDR3 SDRAM Table 19. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GV Parameter <= 667 MHz MDQS epilogue end <= 667 MHz Note: 1. The symbols used for timing specifications follow the pattern ...
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Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t MCK[n] MCK[n] MDQS MDQS Figure 10 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 10. DDR SDRAM ...
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Figure 11 provides the AC test load for the DDR bus. Output 2.7 eSPI This section describes the DC and AC electrical specifications for the eSPI of the MPC8536E. 2.7.1 eSPI DC Electrical Characteristics Table 20 provides the DC ...
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Table 21. SPI AC Timing Specifications Characteristic SPI_CS outputs—Master data (internal clock) delay SPI inputs—Master data (internal clock) input setup time SPI inputs—Master data (internal clock) input hold time Notes: 1. Output specifications are measured from the 50% level of ...
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DUART 2.8 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8536E. 2.8.1 DUART DC Electrical Characteristics Table 22 provides the DC electrical characteristics for the DUART interface. Table 22. DUART DC Electrical ...
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Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps) — FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics The electrical characteristics specified here apply to all FIFO mode, gigabit media independent interface (GMII), media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 25. RGMII, RTBI, and FIFO DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage (LV /TV = Min, IOH = –1.0 mA Output low voltage (LV /TV = ...
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Table 26. FIFO Mode Transmit AC Timing Specification (continued) Parameter/Condition Rise time TX_CLK (20%–80%) Fall time TX_CLK (80%–20%) GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time Note: 1. Data valid t to GTX_CLK Min Setup time is a function ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management RX_CLK t FIRH RXD[7:0] RX_DV RX_ER Figure 15. FIFO Receive AC Timing Diagram 2.9.2.2 GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 2.9.2.2.1 GMII Transmit AC ...
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Figure 16 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER Figure 16. GMII Transmit AC Timing Diagram 2.9.2.2.2 GMII Receive AC Timing Specifications Table 29 provides the GMII receive AC timing specifications. Table 29. GMII Receive AC ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 18 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER 2.9.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 2.9.2.3.1 MII Transmit AC ...
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Figure 19 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER 2.9.2.3.2 MII Receive AC Timing Specifications Table 31 provides the MII receive AC timing specifications. Table 31. MII Receive AC Timing Specifications At recommended operating conditions with ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 21 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 2.9.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 2.9.2.4.1 TBI Transmit AC ...
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Figure 22 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] 2.9.2.4.2 TBI Receive AC Timing Specifications Table 33 provides the TBI receive AC timing specifications. Table 33. TBI Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 23 shows the TBI receive AC timing diagram. TBI Receive Clock 1 (TSECn_TX_CLK) RCG[9:0] TBI Receive Clock 0 (TSECn_RX_CLK) 2.9.2.5 TBI Single-Clock Mode AC Specifications When the eTSEC is configured for TBI ...
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A timing diagram for TBI receive appears in . RX_CLK t TRRH RCG[9:0] Figure 24. TBI Single-Clock Mode Receive AC Timing Diagram 2.9.2.6 RGMII and RTBI AC Timing Specifications Table 35 presents the RGMII and RTBI AC timing specifications. Table ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 25 shows the RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 25. RGMII and RTBI AC ...
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Table 36. RMII Transmit AC Timing Specifications (continued) At recommended operating conditions with L/TV Parameter/Condition Rise time TSECn_TX_CLK (20%–80%) Fall time TSECn_TX_CLK (80%–20%) TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay Note: 1. The symbols used for timing specifications herein follow ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 37. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with L/TV Parameter/Condition Fall time TSECn_RX_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to TSECn_RX_CLK rising edge RXD[1:0], CRS_DV, RX_ER hold time ...
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When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins. 2.9.3.1 DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK The characteristics and DC requirements of ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management 2.9.3.3 SGMII Transmitter and Receiver DC Electrical Characteristics Table 39 and Table 40 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs ...
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Transmitter MPC8536E SGMII SerDes Interface Receiver Figure 29. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8536E SGMII SerDes Interface Transmitter Figure 30. SGMII Transmitter DC Measurement Circuit Table 40. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Table 40. SGMII DC Receiver Electrical Characteristics (continued) Parameter Loss of signal threshold LSTS = 0 LSTS = 1 Input AC common mode voltage Receiver differential input impedance Receiver common mode input impedance ...
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SGMII Receive AC Timing Specifications Table 42 provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is recovered from the data. Figure 31 shows the SGMII Receiver Input Compliance Mask eye diagram. Table 42. ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 32. SGMII AC Test/Measurement Load 2.9.4 eTSEC IEEE 1588 AC Specifications Figure 33 shows the data and command output timing diagram. TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT Figure 33. eTSEC IEEE 1588 Output AC timing ...
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The IEEE 1588 AC timing specifications are in Table 43. eTSEC IEEE 1588 AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition TSEC_1588_CLK clock period TSEC_1588_CLK duty cycle TSEC_1588_CLK peak-to-peak jitter Rise time eTSEC_1588_CLK (20%–80%) Fall time eTSEC_1588_CLK (80%–20%) ...
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Ethernet Management Interface Electrical Characteristics 2.10.1 MII Management DC Electrical Characteristics The EC_MDC and EC_MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for EC_MDIO and EC_MDC are provided in Table 44. MII ...
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Table 45. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition EC_MDIO to EC_MDC hold time EC_MDC rise time EC_MDC fall time Notes: 1. The symbols used for timing specifications herein ...
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USB 2.11.1 USB DC Electrical Characteristics Table 46 provides the DC electrical characteristics for the USB interface. Parameter High-level input voltage Low-level input voltage Input current High-level output voltage, = –100 μ Low-level output voltage, = 100 μA ...
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USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 37. USB Signals USB t USIXKH 65 ...
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Local Bus Controller (eLBC) 2.12 enhanced Local Bus Controller (eLBC) This section describes the DC and AC electrical specifications for the local bus interface of the MPC8536E. 2.12.1 Local Bus DC Electrical Characteristics Table 48 provides the DC electrical ...
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Table 50 provides the DC electrical characteristics for the local bus interface operating at BV Table 50. Local Bus DC Electrical Characteristics (1.8 V DC) Parameter Supply voltage 1.8V High-level input voltage Low-level input voltage Input current 1 (BV = ...
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Local Bus Controller (eLBC) Table 51. Local Bus General Timing Parameters (BV Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance ...
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Table 52. Local Bus General Timing Parameters (BV Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Note: 1. The ...
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Local Bus Controller (eLBC) Table 53. Local Bus General Timing Parameters (BV Parameter Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance ...
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Figure 39 to Figure 42 show the local bus signals. LSYNC_IN Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Output Signals: LA[27:31]/LBCTL/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 39. Local Bus Signals, Non-Special ...
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Local Bus Controller (eLBC) LCLK[n] Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA UPM Mode Input Signal: LUPWAIT t Output Signals: LA[27:31]/LBCTL/LOE t LBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] t LALE Figure 40. Local Bus Signals (PLL Bypass ...
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Table 54. Local Bus General Timing Parameters—PLL Bypassed (continued) Parameter Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD, and LALE Local bus clock to LALE assertion Output hold from local bus clock ...
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Local Bus Controller (eLBC) LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] ...
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LSYNC_IN GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (PLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 42. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] ...
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Enhanced Secure Digital Host Controller (eSDHC) Table 55. eSDHC interface DC Electrical Characteristics (continued) At recommended operating conditions (see Characteristic Symbol Output low voltage V Output high voltage V Output low voltage V Notes: 1. The min V and V ...
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Figure 43 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 43. eSDHC Clock Input Timing Diagram Figure 44 provides the data and command input/output timing diagram. VM SD_CK External Clock SD_DAT/CMD Inputs SD_DAT/CMD Outputs Figure ...
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JTAG Table 57. JTAG DC Electrical Characteristics (continued) Parameter Input current High-level output voltage (OV = min mA Low-level output voltage (OV ...
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Figure 45 provides the AC test load for TDO and the boundary-scan outputs. Output Figure 45. AC Test Load for the JTAG Interface Figure 46 provides the JTAG clock input timing diagram. JTAG External Clock Figure 46. JTAG Clock Input ...
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Serial ATA (SATA) 2.16.1 Requirements for SATA REF_CLK The AC requirements for the SATA reference clock are listed in Table 59. Reference Clock Input Requirements Parameter SD2_REF_CLK/_B reference clock cycle time SD2_REF_CLK/_B frequency tolerance SD_REF_CLK/_B rise/fall time (80%-20%) SD_REF_CLK/_B duty ...
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Differential Transmitter (TX) Output Characteristics Table 60 provides the differential transmitter (TX) output characteristics for the SATA interface. Table 60. Differential Transmitter (TX) Output Characteristics Parameter Channel Speed 1.5G t CH_SPEED 3.0G Unit Interval 1.5G 3.0G DC Coupled Common ...
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Serial ATA (SATA) Table 60. Differential Transmitter (TX) Output Characteristics (continued) Parameter TX Common Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RL SATA_TXCC11 1.2 GHz - 2.4 GHz 2.4 ...
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Differential data lines 20% t SATA_20-80TXrise TX+ TX- t SAT_TXSKEW LATE (TX+ is late) Figure 50. Signal Rise and Fall Times and Differential Skew 2.16.3 Differential Receiver (RX) Input Characteristics Table 61 provides the differential receiver (RX) input characteristics for ...
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Serial ATA (SATA) Table 61. Differential Receiver (RX) Input Characteristics (continued) Parameter Symbol RX Differential Mode Return loss 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RL SATA_RXDD11 1.2 GHz - 2.4 GHz ...
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Out-of-Band (OOB) Electrical Characteristics Table 62 provides the Out-of-Band (OOB) electrical characteristics for the SATA interface of the MPC8536E. Table 62. Out-of-Band (OOB) Electrical Characteristics Parameter OOB Signal Detection Threshold 1.5G 3.0G UI During OOB Signaling COMINIT/ COMRESET and ...
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I C Table 63 recommended operating conditions with OV Parameter Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × and 0.9 × OV ...
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Table 64. I All values refer to V (min) and V (max) levels (see IH IL Parameter Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin ...
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GPIO Figure 52 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 2.18 GPIO This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8536E. 2.18.1 GPIO ...
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GPIO AC Electrical Specifications Table 66 provides the GPIO input and output AC timing specifications. Table 66. GPIO Input and Output AC Timing Specifications Characteristic GPIO inputs—minimum pulse width GPIO outputs—minimum pulse width Notes: 1. Input specifications are measured ...
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PCI 2.19.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 68 provides the PCI AC timing specifications at 66 ...
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Figure 55 shows the PCI input AC timing conditions. CLK Input Figure 55. PCI Input AC Timing Measurement Conditions Figure 56 shows the PCI output AC timing conditions. Output Delay High-Impedance Figure 56. PCI Output AC Timing Measurement Condition 2.20 ...
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High-Speed Serial Interfaces The Differential Input Voltage (or Swing) of the receiver, V voltages Differential Peak Voltage, V The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak ...
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The following sections describe the SerDes reference clock requirements and some application information. 2.20.2.1 SerDes Reference Clock Receiver Characteristics Figure 58 shows a receiver reference diagram of the SerDes reference clocks. • The supply voltage requirements for X2V • SerDes ...
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High-Speed Serial Interfaces 2.20.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8536E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock ...
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Input Amplitude or Differential Peak < 800 _REF_CLK SD n _REF_CLK Figure 60. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV < _REF_CLK Input Amplitude < 800 _REF_CLK ...
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High-Speed Serial Interfaces Figure 62 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8536E SerDes reference clock input’s DC requirement. HCSL ...
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Figure 64 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8536E SerDes reference clock input’s DC requirement, AC-coupling has to ...
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High-Speed Serial Interfaces 2.20.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and ...
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SD n _REF_CLK SD n _REF_CLK Figure 67. Single-Ended Measurement Points for Rise and Fall Time Matching The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application usage. See the following ...
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PCI Express 2.21 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8536E. 2.21.1 DC Requirements for PCI Express SD1_REF_CLK and SD1_REF_CLK For more information, see Section 2.20.2, “SerDes Reference Clocks.” ...
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Table 71. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter V De- Emphasized TX-DE-RATIO Differential Output Voltage (Ratio) T Minimum TX Eye TX-EYE Width T Maximum time TX-EYE-MEDIAN-to- between the jitter MAX-JITTER median and maximum deviation from the median. T ...
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PCI Express Table 71. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter T Maximum time to TX-IDLE-SET-TO-IDLE transition to a valid electrical idle after sending an electrical Idle ordered set T Maximum time to TX-IDLE-TO-DIFF-DATA transition to valid TX specifications ...
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Transmitter Compliance Eye Diagrams The TX eye diagram in Figure 69 any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time ...
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PCI Express 2.21.4.3 Differential Receiver (RX) Input Specifications Table 72 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins. Table 72. Differential Receiver (RX) Input Specifications Symbol Parameter UI Unit ...
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Table 72. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter L Total Skew TX-SKEW Notes test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test ...
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Clocking The reference impedance for return loss measurements is 50. to ground for both the D+ and D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see Figure 71). Note that the series capacitors, CTX, are ...
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Clock Ranges Table 73 provides the clocking specifications for the processor cores and memory bus. Table 73. Processor Core Clocking Specifications Characteristic 600 MHz Min Max e500 core processor 600 600 frequency CCB frequency 400 400 DDR Data Rate ...
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Clocking 2.23.2 CCB/SYSCLK PLL Ratio The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform clock. The frequency of the CCB is set using the following reset signals, as shown ...
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Please note that the DDR PLL reference clock input, DDRCLK, is only required in asynchronous mode. The DDRCLKDR configuration register in the Global Utilities block allows the DDR controller to be run in a divided down mode where the DDR ...
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Thermal 2.23.6 Frequency Options 2.23.6.1 SYSCLK to Platform Frequency Options Table 78 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in comparison to the memory bus clock speed. Table 78. Frequency ...
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Thermal Characteristics Table 79 provides the package thermal characteristics. Characteristic Junction-to-ambient Natural Convection Junction-to-ambient Natural Convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board thermal Junction-to-case thermal Notes 1. Junction temperature is a function of die size, on-chip power dissipation, ...
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Thermal Table 80. MPC8536E Thermal Model (continued) Conductivity Bump/underfill Section A-A A Top View Figure 72. System Level Thermal Model for MPC8536E (Not to Scale) The Flotherm library files of the parts have a dense grid to ...
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Thermal Management Information This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface ...
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System Clocking Figure 74 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Internal Resistance Printed-Circuit Board External Resistance (Note the internal versus external package resistance) Figure 74. ...
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Power Supply Design and Sequencing 3.2.1 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AV AV _PCI, AV _LBIU, and preferably these voltages will ...
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Pin States in Deep Sleep State 3.3 Pin States in Deep Sleep State In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain enabled. The exception is that ...
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Pull-Up and Pull-Down Resistor Requirements The MPC8536E requires weak pull-up resistors (2–10 k Ω is recommended) on open drain type pins including I MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system ...
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Configuration Pin Muxing Local Bus, Ethernet, DUART, Impedance Control, Configuration, Power Management R 45 Target Target P Note: Nominal supply voltages. See Table 3.9 Configuration Pin Muxing The MPC8536E provides the user with power-on configuration options which ...
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The COP interface has a standard header, shown in square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, ...
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JTAG Configuration Signals SRESET From Target Board Sources (if any) HRESET KEY 13 No pin ...
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COP_SRESET COP_HRESET COP_CHKSTP_OUT 3.11 Guidelines for High-Speed Interface Termination 3.11.1 SerDes1 Interface Entirely Unused If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. However, the SerDes must always ...
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Guidelines for High-Speed Interface Termination The following pins must be connected to XGND if not used: • SD1_RX[7:0] • SD1_RX[7:0] • SD1_REF_CLK • SD1_REF_CLK 3.11.3 SerDes 2 Interface Entirely Unused If the high-speed SerDes 2 interface (SGMII/ SATA) is not ...
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Part Numbers Fully Addressed by This Document MPC nnnn E Product Part Security Tiers and Temperature Code Identifier Engine MPC 8536 A = Commercial Tier standard temperature E = included range(0° to 90° Blank =Industrial Tier standard ...
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... MPC8536AVTATH MPC8536AVTAUL MPC8536AVTAVL Standard Temp Extended Temp With Security Without Security MPC8536EBVTAKG MPC8536CVTAKG MPC8536EBVTANG MPC8536CVTANG MPC8536EBVTAQG MPC8536CVTAQG MPC8536EBVTATH MPC8536CVTATH MPC8536EBVTAUL MPC8536CVTAUL MPC8536EBVTAVL MPC8536CVTAVL MPC8536E 29 mm × 783 1 mm 2.23 mm 2.8 mm 96.5Sn/3.5Ag 0.6 mm Notes MPC8536EAVTAKG MPC8536EAVTANG MPC8536EAVTAQG MPC8536EAVTATH MPC8536EAVTAUL MPC8536EAVTAVL Extended Temp ...
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Mechanical Dimensions of the MPC8536E FC-PBGA The mechanical dimensions and bottom surface nomenclature of the MPC8536E, 783 FC-PBGA package are shown in Figure 81. Figure 81. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8536E FC-PBGA 1. All dimensions ...
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Mechanical Dimensions of the MPC8536E FC-PBGA 6 Product Documentation The following documents are required for a complete description of the device and are needed to design properly with the part. • MPC8536E Integrated Processor Reference Manual (document number: MPC8536ERM) • ...
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MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Mechanical Dimensions of the MPC8536E FC-PBGA THIS PAGE INTENTIONALLY BLANK. 127 ...
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter ...