KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet - Page 34

• Manufacturer Part Number: KSZ8864RMNI
• Description: Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
• Manufacturer: MICREL [Micrel Semiconductor]

September 2011
The switch MII interface operates in either MAC mode or PHY mode for KSZ8864RMN. These interfaces are nibble-
wide data interfaces and therefore run at one-quarter the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has
indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a
signal that indicates a collision has occurred during transmission.
Note that the signal MRXER is not provided on the SWx-MII interface and the signal MTXER is not provided on the
SWx-MII interface for both PHY and MAC mode operation. Normally MRXER would indicate a receive error coming
from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not
appropriate for this configuration. For PHY mode operation, if the device interfacing with the KSZ8864RMN has an
MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KSZ8864RMN has an
MTXER pin, it should be tied low.
Switch MAC3/MAC4 SW3/SW4-RMII Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The
KSZ8864RMN supports RMII interface at Port 3 and port 4 switch sides and provides a common interface at MAC3
and MAC4 layer in the device, and has the following key characteristics:
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Table 4 shows two types of RMII connections of MAC to MAC and MAC to PHY,
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When the strap pin P1LED0 is pulled down, the switch MAC4 is SW4-RMII mode after power up reset or warm reset.
When the strap pin P2LED0 is pulled down, the switch MAC3 is SW3-RMII mode after power up reset or warm reset.
Supports 10Mbps and 100Mbps data rates.
Uses a single 50 MHz clock reference (provided internally or externally): in internal mode, the chip provides
reference clock from SMxRXC pin to SMxTXC/SMxREFCLK pin and the reference clock-in pin of the opposite
RMII; in external mode, the chip receives 50MHz reference clock from an external oscillator or opposite RMII
interface to SW4TXC/SM4REFCLK pin only.
Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
The first is an external MAC connects to SW3/4-RMII with ‘PHY mode’.
The second is an external PHY connects to SW3/4-RMII with ‘MAC mode’.
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