ATAM894X-TNQY ATMEL [ATMEL Corporation], ATAM894X-TNQY Datasheet - Page 71
ATAM894X-TNQY
Manufacturer Part Number
ATAM894X-TNQY
Description
8k-flash Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM894X-TNQY.pdf
(97 pages)
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6.3.4.16
6.3.5
6.3.5.1
Figure 6-48. Combination Timer 2 and SSI
4679D–4BMCU–05/05
Combination Modes
Serial Receive Buffer (SRB) – Byte Read
Combination Mode Timer 2 and SSI
T2I
SYSCL
T1OUT
TOG3
SCL
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant
bit first) and the loads content into the receive buffer when the complete telegram has been
received.
The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multi-
tude of modes in which the timers and serial interface can work together.
The 8-bit wide serial interface operates as shift register for modulation and demodulation. The
modulator and demodulator units work together with the timers and shift the data bits into or out
of the shift register.
First read cycle
Second read cycle
T2C
CL2/1
I/O-bus
RES
4-bit Counter 2/1
Compare 2/1
T1OUT
SYSCL
T2CO1
POUT
P4CR
TOG2
OVF1
SIC1
SCLI
SCL
POUT
TOG2
POUT
Bit 7
Bit 3
Timer 2 - control
Shift_CL
CM1
CL2/2
SO
T2M1
T2CM
SIC2
Transmit
buffer
Bit 6
Bit 2
MSB
DCG
STB
SSI-control
8-bit shift register
DCGO
RES
8-bit Counter 2/2
I/O-bus
Compare 2/2
Bit 5
Bit 1
T2CO2
SISC
SRB
I/O-bus
OVF2
LSB
Receive
buffer
TOG2
INT4
Bit 4
Bit 0
Control
SI
INT3
SO
Output
MOUT
SO
Manchester
OUTPUT
modulator
Bi-phase
T2M2
Primary register address: '9'hex
Control
MCL_SC
MCL_SD
output-stage
modulator
Reset value: xxxxb
Reset value: xxxxb
Timer 2
T2O
SD
SC
ATAM894
71
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