MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 50

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 13. SPI Register Overview
parameters (e.g. ICG trim value) are stored in the flash
memory of the device. The following flash memory locations
are reserved for this purpose and might have a value different
from the “empty” ($FF) state:
• $FD80:$FDDF Trim and Calibration Values
• $FFFE :$FFFF Reset Vector
has to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
Trim Values
is explained by the following.
Internal Clock Generator (ICG) Trim Value
create a stable clock source for the microcontroller, without
using any external components. The untrimmed frequency of
the low frequency base clock (IBASE) will vary as much as
±25 percent due to process, temperature, and voltage
dependencies. To compensate these dependencies, a ICG
trim value is located at address $FDC2. After trimming, the
ICG is in a range of typ. ±2% (±3% max.) at nominal
conditions (filtered (100nF), and stabilized (4.7μF) V
T
(V
Register ICGTR at address $38 of the MCU.
50
908E622
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Ambient
$10
$11
DD
To enhance the ease-of-use of the 908E622, various
In the event the application uses these parameters, one
The usage of the trim values located in the flash memory
The internal clock generator (ICG) module is used to
To trim the ICG, this value has to be copied to the ICG Trim
Important The value has to copied after every reset.
), as indicated in the 68HC908EY16 datasheet.
~25°C), and will vary over temperature and voltage
Table 14. Window Clear Interval
Window
$FDCF
Range
System Trim 2
System Trim 3
0
(SYSTRIM2)
(SYSTRIM3)
Select bits
WDP1:0
Period
00
01
10
11
min.
W
W
8.5
68
34
17
R
R
Watchdog Period
CRHBHC1 CRHBHC0
CRHBHC3 CRHBHC2
FACTORY TRIMMING AND CALIBRATION
max.
11.5
t_wd
0
0
92
46
23
Unit
DD
ms
0
0
= 5V,
t_open
11.5
5.75
Effective Open Window
CRHB5
CRHS5
46
23
0
0
Watchdog Period Range Value (AWD Trim)
from code runaways).
the open window. Due to the high variation of the watchdog
period, and therefore the reduced width of the watchdog
window, a value is stored at address $FDCF. This value
classifies the watchdog period into 3 ranges (Range 0, 1, 2).
It allows the application software to select one of three time
intervals to clear the watchdog based on the stored value.
The classification is done in a way that the application
software can have up to ±19% variation of the of optimal clear
interval, e.g. caused by ICG variation.
Effective Open Window
with a 50% open window, results in an effective open window,
which can be calculated by:
Optimal Clear Interval
the biggest possible variation to latest window open time, and
to the earliest window closed time, can be calculated with the
following formula:
watchdog based on the Window No. and chosen period.
The window watchdog supervises device recovery (e.g.
The application software has to clear the watchdog within
Having a variation in the watchdog period in conjunction
latest window open time: t_open = t_wd max / 2
earliest window closed time: t_closed = t_wd min
The optimal clear interval, meaning the clear interval with
t_opt = t_open + (t_open+t_closed) / 2
See
t_closed
8.5
68
34
17
CRHB4
CRHS4
Table 14
0
0
Unit
ms
to select the optimal clear interval for the
CRHB3
CRHS3
0
0
Analog Integrated Circuit Device Data
t_opt
14.25
7.125
28.5
57
Optimal Clear Interval
CRHB2
CRHS2
0
0
Freescale Semiconductor
Unit
ms
CRHB1
CRHS1
variation
±19.3%
0
0
max.
CRHB0
CRHS0
0
0