XC2V2000-5FG256C XILINX [Xilinx, Inc], XC2V2000-5FG256C Datasheet - Page 75

• Manufacturer Part Number: XC2V2000-5FG256C
• Description: Virtex-II Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in
Table 30: Power-Up Timing Characteristics
Master/Slave Serial Mode Parameters
Clock timing for Slave Serial configuration programming is shown in
Figure
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied
Power-on reset
Program latency
CCLK (output) delay
Program pulse width
directly to ground or V
4. Programming parameters for both Slave and Master modes are given in
R
Description
M0, M1, M2*
CCAUX
PROG_B
(Required)
or Input)
INIT_B
(Output
CCLK
V
. The mode pins should not be toggled during and after configuration.
CC
Figure 2: Configuration Power-Up Timing
References
Figure
*Can be either 0 or 1, but must not toggle during and after configuration.
1
2
3
Figure
www.xilinx.com
1
T
POR
Virtex-II Platform FPGAs: DC and Switching Characteristics
2; corresponding timing characteristics are listed in
2
T
PL
T
Symbol
PROGRAM
T
T
T
ICCK
POR
PL
Figure
3, with Master Serial clock timing shown in
T
ICCK
Table
3
T
Value
PL
300
0.5
4.0
4
31.
ds083-3_07_012004
+ 2
μs per frame, max
ms, max
μs, max
μs, min
ns, min
Units
Module 3 of 4
Table
30.
27