EP1C20F ALTERA [Altera Corporation], EP1C20F Datasheet - Page 21
EP1C20F
Manufacturer Part Number
EP1C20F
Description
Cyclone FPGA Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EP1C20F.pdf
(106 pages)
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Altera Corporation
May 2008
Figure 2–10. LUT Chain and Register Chain Interconnects
The C4 interconnects span four LABs or M4K blocks up or down from a
source LAB. Every LAB has its own set of C4 interconnects to drive either
up or down.
LAB in a column. The C4 interconnects can drive and be driven by all
types of architecture blocks, including PLLs, M4K memory blocks, and
column and row IOEs. For LAB interconnection, a primary LAB or its
LAB neighbor can drive a given C4 interconnect. C4 interconnects can
drive each other to extend their range as well as drive row interconnects
for column-to-column connections.
Interconnect
Figure 2–11
Adjacent LE
Routing to
LUT Chain
Local
shows the C4 interconnect connections from a
Local Interconnect
Routing Among LEs
in the LAB
LE 10
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
Register Chain
Routing to Adjacent
LE's Register Input
MultiTrack Interconnect
Preliminary
2–15