ADMC328TN AD [Analog Devices], ADMC328TN Datasheet - Page 16

• Manufacturer Part Number: ADMC328TN
• Description: 28-Lead ROM-Based DSP Motor Controller with Current Sense
• Manufacturer: AD [Analog Devices]

ADMC328
The second method for detecting a fault condition is through
the I
pin monitors the feedback signals from a dc bus current sensing
resistor that represents the total current in the motor. When the
voltage of I
will be internally pulled low. The negative edge of the internal
PWMTRIP will generate a shutdown in the same manner as a
negative edge on pin PWMTRIP.
It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the PWMTRIP or I
shutdown, it is possible to determine if the shutdown was gener-
ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that PWMTRIP returns to a HI state and I
to a voltage greater than the I
has been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB and PWMCHC. After the fault
is cleared and the PWM registers are initialized, internal timing
of the three-phase timing unit will resume, and the new duty cycle
values will be latched on the next rising edge of PWMSYNC.
PWM Registers
The configuration of the PWM registers is described at the end
of the data sheet. The parameters of the 16-bit PWM Timer is
tabulated in Table V.
ADC OVERVIEW
The ADC of the ADMC328 is based upon the single slope
conversion technique. This approach offers an inherently
monotonic conversion process and, to within the noise and sta-
bility of its components, there will be no missing codes.
Select
VAUX0
VAUX1
VAUX2
Calibration (V
16-BIT PWM TIMER
Parameter
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
Gate Drive Chop Frequency Range
SENSE
Table VI. ADC Auxiliary Channel Selection
pin in the analog block of the ADMC328. The I
SENSE
REF
)
goes below I
Table V. Fundamental Characteristics of PWM Generation Unit of ADMC328
MODECTRL (1)
ADCMUX1
0
0
1
1
SENSE
CRST
SENSE
SENSE
)
trip threshold. After the fault
trip threshold, PWMTRIP
pins. Following a PWM
MODECTRL (0)
ADCMUX0
0
1
0
1
SENSE
returns
SENSE
–16–
The single slope technique has been adapted on the ADMC328
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. Two of the
main inputs (V1 and V2) are directly connected as high imped-
ance voltage inputs. The third main input channel (I
special design to monitor the voltage on a current-sensing resis-
tor whose voltage is always below (more negative than) GND. The
fourth channel has been configured with a serially-connected
4-to-1 multiplexer. Table VI shows the multiplexer input selection
codes. One of these auxiliary multiplexed channels is used to cali-
brate the ramp against the internal voltage reference (V
Comparing each ADC input to a reference ramp voltage, and tim-
ing the comparison of the two signals, performs the conversion
process. The actual conversion point is the time point intersec-
tion of the input voltage and the ramp voltage (V
Figure 12. This time is converted to counts by the 12-bit ADC
Timer Block and is stored in the ADC registers. The ramp volt-
age used to perform the conversion is generated by driving a
fixed current into an off-chip capacitor, where the capacitor
voltage is
C
GND
EXTERNAL
CHARGING
CAP
ICONST
VAUX2
I
VAUX0
VAUX1
SENSE
V2
V1
Min
0
150
0.05
0.02
–5 X
V
C
Figure 11. ADC Overview
0.8 X
4 – 1
MUX
V
COMP
COMP
Typ
16
100
50
100
0
100
C
= (I/C)
COMP
COMP
COMP
ICONST_TRIM<2:0>
(CAP RESET)
V1L
V2L
V3L
VAUXL
t
PWMTRIP
Max
100
100
12.5
5
BLOCK
REGISTERS
12-BIT
TIMER
ADC
V
ADC
REF
PWMSYNC (CONVST)
C
CLK MODECTRL<7>
) as shown in
ADC REGISTERS
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
Unit
Bits
ns
ns
ns
ns
Hz
MHz
SENSE
REF
s
s
s
).
REV. B
) has a