ADSP21MOD980N AD [Analog Devices], ADSP21MOD980N Datasheet - Page 13

• Manufacturer Part Number: ADSP21MOD980N
• Description: MultiPort Internet Gateway Processor
• Manufacturer: AD [Analog Devices]

ever, to write to the processor’s memory-mapped control
registers. A typical IDMA transfer process is described as
follows:
1.
2.
1.
2.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written to, while the
ADSP-21mod980N is operating at full speed.
The processor memory address is latched and then auto-
matically incremented after each IDMA transaction. An
external device can therefore access a block of sequentially
addressed memory by specifying only the starting address of
the block. This increases throughput as the address does
not have to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is
asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address
REV. PrB 6/2001
Host starts IDMA transfer
Host uses IS and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the processor’s IDMA control
registers.
If IAD [15] = 1, the value of IAD [7:0] represents the
IDMA overlay: IAD[14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represents the
starting address of internal memory to be accessed and
IAD [14] reflects PM or DM for access.
Host uses IS and IRD (or IWR) to read (or write) pro-
cessor internal memory (PM or DM).
Host ends IDMA transfer.
RESE RVE D
ALW A YS SET
TO 0
RESE RVE D
ALW A YS SET
TO 0
PRELIMINARY TECHNICAL DATA
15
15
0
0
For current information contact Analog Devices at (800) ANALOGD
14
14
U
0
Short R ead O nly
En able
1 = Enable
0 = D isable
IDM AD
Destination m em ory type:
0=PM
1=DM
13
13
U
0
12
12
U
Figure 9. IDMA Control/OVLAY Registers
IDM A CO NTR O L (U=U ND EF IN ED AT R ESE T)
0
RESE RVE D
SET TO 0
11
11
U
0
10
10
U
0
IDM A O V ER LA Y
9
9
U
0
8
8
U
0
IDM AA
ADDR ESS
7
0
7
U
specifies an on-chip memory location, the destination type
specifies whether it is a DM or PM access. The falling edge
of the address latch signal latches this value into the
IDMAA register.
Once the address is stored, data can then be either read
from, or written to, the ADSP-21mod980N’s on-chip
memory. Asserting the select line (IS) and the appropriate
read or write line (IRD and IWR respectively) signals the
ADSP-21mod980N that a particular transaction is
required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is auto-
matically incremented, and another access can occur.
Through the IDMAA register, the processor can also spec-
ify the starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch
enable (IAL) directs the ADSP-21mod980N to write the
address onto the IAD [14:0] bus into the IDMA Control
Register. If IAD [15] is set to 0, IDMA latches the address.
If IAD [15] is set to 1, IDMA latches OVLAY memory. The
IDMAA register is memory mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) or over-
lay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address
DM(0x3FE7). See
tion on IDMA memory mapping. When bit 14 in 0x3FE7
is set to 1, then timing in
short reads. When bit 14 in 0x3FE7 is set to zero short
reads use the timing shown in
ID DM O VLAY
0
6
6
U
5
0
5
U
4
0
4
U
3
3
U
0
ID PM O VLAY
Figure on page 13
2
2
U
0
1
1
U
0
Figure on page 35
0
0
U
0
ADSP-21mod980N
Figure on page
DM (0x3FE7)
DM (0x3FE0)
for more informa-
applies for
34.
13