ADSP21020 AD [Analog Devices], ADSP21020 Datasheet - Page 25

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ADSP21020

Manufacturer Part Number
ADSP21020
Description
32/40-Bit IEEE Floating-Point DSP Microprocessor
Manufacturer
AD [Analog Devices]
Datasheet

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REV. C
Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF
on address, select, page and strobe pins, and 50 pF on all others
(see Figure 14). For different loads, these timing parameters
should be derated. See the Hardware Configuration chapter of
the ADSP-21020 User’s Manual for further information on
derating of timing specifications.
Figures 16 and 17 show how the output rise time varies with
capacitance. Figures 18 and 19 show how output delays vary
with capacitance. Note that the graphs may not be linear outside
the ranges shown.
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 16. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
Figure 17. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
4
3
2
1
0
25
10
4
3
2
1
0
9
8
7
6
5
1.33
0.85
25
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
1.46
1.31
50
50
75
LOAD CAPACITANCE – pF
75
LOAD CAPACITANCE – pF
100
100
125
125
150
1
2
150
1
2
175
175
3.59
3.00
9.18
3.95
200
200
–25–
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
NOMINAL
Figure 18. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
NOMINAL
Figure 19. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
12
10
–2
–1
–2
–3
8
6
4
2
3
2
1
25
25
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
– 1.70
– 0.89
– 2.24
–1.86
50
50
75
75
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
100
100
125
125
ADSP-21020
1
2
150
150
1
2
175
175
11.19
2.99
2.27
5.34
200
200

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