ADSP-21363SBBC-ENG AD [Analog Devices], ADSP-21363SBBC-ENG Datasheet - Page 18

• Manufacturer Part Number: ADSP-21363SBBC-ENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21363
Clock Input
Table 11. Clock Input
1
2
3
Clock Signals
The ADSP-21363 can use an external clock or a crystal. See
CLKIN pin description in
can configure the ADSP-21363 to use its internal clock genera-
tor by connecting the necessary components to CLKIN and
XTAL.
crystal operating in fundamental mode. Note that the clock rate
is achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
CLKIN
3
Figure 8
Figure 8. 333 MHz Operation (Fundamental Mode Crystal)
C1
CLKIN
shows the component connections used for a
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4V–2.0V)
CCLK Period
1M
X1
t
Figure 7. Clock Input
CKH
Table 3 on Page
C2
XTAL
t
CK
t
CKL
10. The programmer
Rev. PrA | Page 18 of 44 | September 2004
Min
18
7.5
7.5
3.0
1
1
1
1
CCLK
.
333 MHz
Preliminary Technical Data
Max
TBD
TBD
TBD
TBD
TBD
2
2
2
Unit
ns
ns
ns
ns
ns