DSP56004/D FREESCALE [Freescale Semiconductor, Inc], DSP56004/D Datasheet - Page 31

• Manufacturer Part Number: DSP56004/D
• Description: SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
MOTOROLA
Note:
No.
16a Minimum Edge-triggered Interrupt Request
10
14
15
16
22
25
27
18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid
RESET
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (C
Minimum RESET assertion width:
Mode Select Setup Time
Mode Select Hold Time
Minimum Edge-triggered Interrupt Request Assertion
Width
Deassertation Width
Caused by First Interrupt Instruction Execution
Delay from General Purpose Output Valid to Interrupt
Request Deassertation for Level Sensitive Fast
Interrupts—If Second Interrupt Instruction is:
Duration of IRQA Assertion for Recovery from Stop State
Duration for Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting “Stop”)
1.
2.
•
•
•
•
•
•
This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP
pin. For capacitor values 2 nF, asserting RESET according to this timing requirement will ensure
proper processor initialization for capacitors with a C/C < 0.5%. (This is typical for ceramic
capacitors.) For capacitor values > 2 nF, asserting RESET according to this timing requirement will
ensure proper processor initialization for capacitors with a C/C < 0.01%. (This is typical for Teflon,
polystyrene, and polypropylene capacitors.) However, capacitors with values > 2 nF with a
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered
mode is recommended when using fast interrupts. Long interrupts are recommended when using
Level-sensitive mode.
C/C > 0.01% may require longer RESET assertion to ensure proper initialization.
PLL disabled
PLL enabled
Single Cycle
Two Cycles
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
Freescale Semiconductor, Inc.
For More Information On This Product,
1
Characteristics
Go to: www.freescale.com
Figure 2-2 Reset Timing
DSP56004/D, Rev. 3
10
2
RESET, Stop, Mode Select, and Interrupt Timing
12
2500
6
25
Min
T
T
21
13
13
12
12
C
0
C
L
T
All frequencies
+ T
ET
+ T
C
= 50 pF + 2 TTL Loads)
C
L
H
(2
T
T
C
Max
L
) + T
—
—
—
—
—
—
—
—
—
—
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Specifications
L
– 31
V
AA0251
IHR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-7