ISL78420 INTERSIL [Intersil Corporation], ISL78420 Datasheet - Page 12

• Manufacturer Part Number: ISL78420
• Description: 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time
• Manufacturer: INTERSIL [Intersil Corporation]

Power Dissipation
The dissipation of the ISL78420 is dominated by the gate charge
required by the driven bridge FETs and the switching frequency.
The internal bias and boot diode also contribute to the total
dissipation but these losses are usually insignificant compared to
the gate charge losses.
The calculation of the power dissipation of the ISL78420 is very
simple.
GATE POWER (FOR THE HO AND LO OUTPUTS)
where
Q
Freq is the switching frequency.
BOOT DIODE DISSIPATION
where 0.6V is the diode conduction voltage
BIAS CURRENT
where I
switching frequency
TOTAL POWER DISSIPATION
P
OPERATING TEMPERATURES
T
where T
temperature, T
T
where T
temperature of the PCB, T
soldered.
P
I
P
P
diode_avg
j
j
gate
total
gate
diode
bias
= P
= P
total
total
is the charge of the driven bridge FET at VDD, and
= P
=
=
bias
=
j
j
I
4 Q
is the junction temperature at the operating air
is the junction temperature with the operating
bias
gate
I
x
x
×
diode_avg
=
is the internal bias current of the ISL78420 at the
θ
θ
Q
JA
JC
×
gate
+ P
amb
gate
VDD
+ T
+ T
diode
×
amb
, in the vicinity of the part.
PCB
×
Freq
×
Freq
0.6V
+ P
×
PCB
bias
VDD
12
, as measured where the EPAD is
ISL78420
(EQ. 3)
(EQ. 4)
(EQ. 5)
(EQ. 6)
PC Board Layout
The AC performance of the ISL78420 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the ISL78420:
• Understand well how power currents flow. The high amplitude
• Keep power loops as short as possible by paralleling the
• Use planes where practical; they’re usually more effective than
• Planes can also be non-grounded nodes.
• Avoid paralleling high di/dt traces with low level signal lines.
• When practical, minimize impedances in low level signal
• Be aware of magnetic fields emanating from transformers and
• If you must have traces close to magnetic devices, align the
• The use of low inductance components such as chip resistors
• Use decoupling capacitors to reduce the influence of parasitic
• It may be necessary to add resistance to dampen resonating
• Keep high dv/dt nodes away from low level circuits. Guard
• Avoid having a signal ground plane under a high dv/dt circuit.
• Do power dissipation and voltage drop calculations of the
• Large power components (Power FETs, Electrolytic capacitors,
• If you simulate your circuits, consider including parasitic
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
source and return traces.
parallel traces.
High di/dt will induce currents in the low level signal lines.
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
inductors. Core gaps in these structures are especially bad for
emitting flux.
traces so that they are parallel to the flux lines.
and chip capacitors is recommended.
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
parasitic circuits. In PCB designs with long leads on the LO and
HO outputs, it may be necessary to add series gate resistors on
the bridge FETs to dampen the oscillations.
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
This will inject high di/dt currents into the signal ground paths.
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
components.
September 24, 2012
FN8296.1