PCM61 BURR-BROWN [Burr-Brown Corporation], PCM61 Datasheet - Page 4

• Manufacturer Part Number: PCM61
• Description: Serial Input 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

FIGURE 1. PCM61P Timing Diagram.
FIGURE 2. PCM61P Setup and Hold Timing Diagram.
MAXIMUM CLOCK RATE
The maximum clock rate of 16.9MHz for the PCM61P is
derived by multiplying the standard audio sample rate of
44.1kHz times sixteen (16 x oversampling) times the standard
audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9MHz).
Note that this clock rate accommodates a 24-bit word length,
even though only 18 bits are actually being used.
FIGURE 3. MSB Adjust Circuit.
Enable
Clock
Latch
Input
Data
NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream.
(2) Data format is binary two‘s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain
low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative.
Input
MSB Adjust 14
P17 (Latch Enable)
Trim 15
>25ns
> One Clock Cycle
>15ns >15ns
®
P16 (Clock)
P18 (Data)
>60ns
PCM61P
>25ns
LSB
470k
>25ns
100k
MSB
1
>5ns
>15ns
> One Clock Cycle
2
200k
3
MSB
4
1 –V
S
10
4
11
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM61P can be adjusted to make the
differential linearity error (DLE) at BPZ essentially zero. This
is important when the signal output levels are very low,
because zero crossing noise (DLE at BPZ) becomes very
significant when compared to the small code changes occur-
ring in the LSB portion of the converter.
To statically adjust DLE at BPZ, refer to the circuit shown in
Figure 3 or the PCM61P connection diagram.
Differential linearity error at bipolar zero and THD are guar-
anteed to meet data sheet specifications without any external
adjustment. However, a provision has been made for an
optional adjustment of the MSB linearity point, which makes
it possible to eliminate DLE error at BPZ. Two procedures are
given to allow either static or dynamic adjustment. The
dynamic procedure is preferred because of the difficulty
associated with the static method (accurately measuring 16-
bit LSB steps).
After allowing ample warm-up time (5-10 minutes) to assure
stable operation of the PCM61P, select input code 3FFFF
hexadecimal (all bits on except the MSB). Measure the output
voltage using a 6-1/2 digit voltmeter and record it. Change the
digital input code to 00000 hexadecimal (all bits off except the
MSB). Adjust the 100k
read 22.9 V more than the voltage reading of the previous
code (a 1LSB step = 22.9 V). A much simpler method is to
dynamically adjust the DLE at BPZ. Assuming the device has
been installed in a digital audio application circuit, send the
appropriate digital input to produce a –60dB level sinusoidal
output, then adjust the 100k potentiometer until a minimum
level of distortion is observed.
12
13
14
15
potentiometer to make the output
16
17
LSB
18
1