DAC667JP BURR-BROWN [Burr-Brown Corporation], DAC667JP Datasheet - Page 8

• Manufacturer Part Number: DAC667JP
• Description: Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

TABLE III. Output Voltage Range Connections.
FIGURE 9. 12-Bit Data Formats for 8-Bit Systems.
Whenever a 12-bit D/A is loaded from an 8-bit bus, two
bytes are required. If the software program considers the
data to be a 12-bit binary fraction (between 0 and 4095/
4096), the data is left-justified, with the eight most signifi-
cant bits in one byte and the remaining bits in the upper half
of another byte. Right-justified data calls for the eight least
significant bits to occupy one byte, with the four most
significant bits residing in the lower half of another byte,
simplifying integer arithmetic.
Figure 10 shows an addressing scheme for use with a DAC-
667 set up for left-justified data in an 8-bit system. The base
address is decoded from the high-order address bits and the
resultant active-low signal is applied to CS. The two LSBs
of the address bus are connected as shown to the DAC667
address inputs. The latches now reside in two consecutive
locations, with location X01 loading the four LSBs and
location X10 loading the eight MSBs and updating the output.
0 to +10V
OUTPUT
0 to +5V
RANGE
DB11 DB10
DB3
DB7
2.5V
10V
X
5V
DB2
DB6
®
X
DAC667
DB9
DB1
DB5
X
INPUT CODES
Straight Binary
Straight Binary
Offset Binary
Offset Binary
Offset Binary
(b) Right-Justified
(a) Left-Justified
DIGITAL
DB8
DB0
DB4
X
DB11 DB10
DB7
DB3
X
DB6
DB2
X
CONNECT
PIN 9 TO
1 and 2
1 and 2
DB5
DB9
DB1
1
2
2
X
DB4
DB8
DB0
X
CONNECT
PIN 1 TO
2 and 9
2 and 9
9
3
3
8
FIGURE 10. Left-Justified 8-Bit Bus Interface.
Right-justified data can also be accommodated as shown in
Figure 11. The DAC667 still occupies two adjacent loca-
tions in the processor’s memory map. Location X01 loads
the eight LSBs and location X10 loads the four MSBs and
updates the output.
12- AND 16-BIT BUS INTERFACES
For operation with 12- and 16-bit buses, all four address
lines (A0 through A3) are connected to logic 0, and the latch
is enabled by CS asserted low. The DAC667 thus occupies
a single memory location.
This configuration uses the first and second rank registers
simultaneously. The CS input can be driven from an active-
low decoded address. It should be noted that any data bus
activity during the period when CS is low will cause activity
at the DAC667 output. If data is not guaranteed stable during
this period, the second rank register can be used to provide
double buffering. See Figure 12.
CONNECT
PIN 2 TO
1 and 9
1 and 9
A15
WR
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
NC
9
9
Address
Decoder
CONNECT PIN 4 TO
6 (Through 50 fixed or 100 trim resistor.)
6 (Through 50 fixed or 100 trim resistor.)
6 (Through 50 fixed or 100 trim resistor.)
5 (Or optional trim. See Figure 7.)
5 (Or optional trim. See Figure 7.)
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
CS
A0
A1
A2
A3
DAC667