X9260 INTERSIL [Intersil Corporation], X9260 Datasheet - Page 5

• Manufacturer Part Number: X9260
• Description: Dual Supply/Low Power/256-Tap/SPI bus
• Manufacturer: INTERSIL [Intersil Corporation]

PRINCIPLES OF OPERATION
Serial Interface
The X9260 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9260 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(R
Figure 1.
H
IF WCR = 00[H] THEN R
IF WCR = FF[H] THEN R
and R
One of Two Potentiometers
FROM INTERFACE
SERIAL DATA PATH
.
L
Detailed Potentiometer Block Diagram
CIRCUITRY
inputs).
W
W
= R
= R
5
L
H
REGISTER 0
REGISTER 2
(DR0)
(DR2)
8
REGISTER 1
REGISTER 3
MODIFIED SCK
(DR1)
(DR3)
X9260
UP/DN
8
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
Power-up and Down Requirements.
At all times, the voltages on the potentiometer pins
must be less than V+ and more than V-. During power-
up and power-down, VCC, V+, and V- must reach their
final values within 1msecs of each other. The V
ramp rate spec is always in effect.
W
SERIAL
BUS
INPUT
UP/DN
CLK
BUS
INPUT
) output. Within each individual array only one
PARALLEL
REGISTER
COUNTER
INC/DEC
WIPER
(WCR)
LOGIC
C
O
U
N
T
E
R
D
E
C
O
D
E
R
R
R
February 28, 2005
H
L
W
FN8170.0
CC