X9420-2.7 INTERSIL [Intersil Corporation], X9420-2.7 Datasheet
X9420-2.7
Related parts for X9420-2.7
X9420-2.7 Summary of contents
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... A0 1 Low Noise/Low Power/SPI Bus March 7, 2005 DESCRIPTION The X9420 integrates a single digitally controlled potentiometers (XDCP monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches ...
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... The SCK input is used to clock data into and out of the X9420. Chip Select (CS) When CS is HIGH, the X9420 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9420, placing it in the active power mode ...
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... Finally loaded with the contents of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9420 is powered- down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down ...
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... Write In Process bit (WIP). The WIP bit is read with a Read Status command. INSTRUCTIONS Address/Identification (ID) Byte The first byte sent to the X9420 from the host, following a CS going HIGH to LOW, is called the Address or Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9420 this is fixed as 0101[B] (refer to Figure 2) ...
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... These instructions transfer data between 1 0 the host and the X9420; either between the host and one of the Data Registers or directly between the host and the WCR. These instructions are: – Read Wiper Counter Register—read the current wiper position of the pot, – ...
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... CS SCL Figure 7. Increment/Decrement Instruction Sequence CS SCK Figure 8. Increment/Decrement Timing Limits SCK INC/DEC CMD Issued 6 X9420 Voltage Out Don’ ...
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... XFR Data Register Wiper Counter Register XFR Wiper Counter 1 1 Register to Data Register Increment/Decrement 0 0 Wiper Counter Register Read Status (WIP bit X9420 Instruction Set Read the contents of the Wiper Counter Register 1 0 ...
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... X9420 on SO instruction opcode (sent by Host on SI instruction register opcode addresses (sent by X9420 on SO instruction register Data Byte opcode addresses (sent by host on SI) ...
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... Rising R R Edge instruction increment/decrement opcode (sent by master on SDA I/D I/D . instruction Data Byte opcode (sent by X9420 on SO HIGH-VOLTAGE WRITE CYCLE CS Rising Edge . . . I/D I/D CS Rising W Edge I P FN8195.0 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Max. Device +70°C X9420 +85°C X9420-2.7 Limits Min. Typ. 150 40 X9420 +4.5 X9420-2.7 +2.7 X9420 -5.5 X9420-2.7 -5 -140 1.6 ±300 TOTAL 10/10/25 0.1 Supply Voltage (V ) Limits CC 5V ± 10% 2 ...
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... Notes: (5) This parameter is periodically sampled and not 100% tested. (6) t and t are the delays required from the time the third (last) power supply (V PUR PUW can be issued. These parameters are periodically sampled and not 100% tested. 11 X9420 Limits Min. Typ. Max. 400 1 1 ...
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... HOLD High to Output in Low Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs Deselect Time CS t WP, A0 and A1 Setup Time WPASU t WP, A0 and A1 Hold Time WPAH 12 X9420 EQUIVALENT A.C. LOAD CIRCUIT 0.5 Parameter 5V 1533Ω SDA Output 100pF Min. Max. Units 2.0 ...
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... High High May change Will change from High to from High to Low Low Don’t Care: Changing: Changes State Not Allowed Known N/A Center Line is High Impedance 13 X9420 Parameter Parameter Typ. Max. Units Min. Max. Units 10 µs 10 µs 450 ns FN8195.0 March 7, 2005 ...
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... TIMING DIAGRAMS Input Timing CS t LEAD SCK MSB SI High Impedance SO Output Timing CS SCK t V MSB SO ADDR SI Hold Timing CS SCK HOLD 14 X9420 t CYC ... ... ... t HO ... t t HSU HH ... HOLD LAG t RI LSB t DIS ...
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... XDCP Timing (for All Load Instructions) CS SCK MSB High Impedance SO XDCP Timing (for Increment/Decrement Instruction) CS SCK ADDR High Impedance SO Write Protect and Device Address Pins Timing X9420 ... ... ... t WRID ... ... Inc/Dec Inc/Dec (Any Instruction WPAH WPASU t WRL LSB March 7, 2005 FN8195.0 ...
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... V OP- – -5V Voltage Regulator V 317 adj (REG) = 1.25V (1 adj 2 16 X9420 V W Cascading Techniques + OUT (a) Offset Voltage Adjustment (REG 100kΩ – + TL072 10kΩ 10kΩ ...
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... PACKAGING INFORMATION 16-Lead Hermetic Dual In-Line Package Type D Seating Plane 0.200 (5.08) 0.150 (3.81) Min. 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) Typ. 0.100 (2.54) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 17 X9420 0.735 (18.67) 0.775 (19.69) Pin 1 0.700 (17.78) Ref. 0.065 (1.65) 0.038 (0.97) Typ. 0.060 (1.52) 0.320 (8.13) 0.290 (7.37) Typ. 0.311 (7.90) 0.015 (0.38) 0.008 (0.20) 0.310 (7.87) ...
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... PACKAGING INFORMATION 16-Lead Plastic SOIC (300 Mil Body) Package Type S PIN 1 INDEX PIN 1 (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° ° 0.015 (0.40) 0.050 (1.27) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 18 X9420 0.014 (0.35) 0.020 (0.51) 0.403 (10.2 ) 0.413 ( 10.5) X 45° 0.0075 (0.19) 0.420" 0.010 (0.25) FOOTPRINT 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) ...
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... PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X9420 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) .019 (.50) .029 (.75) Detail A (20X) .252 (6.4) BSC .047 (1.20) Gage Plane Seating Plane ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 X9420 ...