ADV7343 AD [Analog Devices], ADV7343 Datasheet - Page 77
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ADV7343
Manufacturer Part Number
ADV7343
Description
Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
Manufacturer
AD [Analog Devices]
Datasheet
1.ADV7343.pdf
(88 pages)
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Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the
S_HSYNC and S_VSYNC pins, respectively.
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and
S_VSYNC pins, respectively.
HSYNC
HSYNC
FIELD
FIELD
622
309
DISPLAY
DISPLAY
HSYNC
FIELD
PIXEL
DATA
623
310
624
311
EVEN FIELD
ODD FIELD
625
312
Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
ODD FIELD
EVEN FIELD
313
1
314
2
Figure 105. SD Slave Mode 1, PAL
315
3
Rev. 0 | Page 77 of 88
VERTICAL BLANK
VERTICAL BLANK
316
4
317
5
318
6
319
7
NTSC = 122 × CLOCK/2
PAL = 132 × CLOCK/2
320
Cb
21
Y
ADV7342/ADV7343
334
22
Cr
Y
DISPLAY
335
23
DISPLAY
336