ADV7181CBCPZ-REEL AD [Analog Devices], ADV7181CBCPZ-REEL Datasheet - Page 9

• Manufacturer Part Number: ADV7181CBCPZ-REEL
• Description: 10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
3, 10, 24, 57
32, 37, 43
4, 11
23, 58
40
31
34
35, 36, 46, 47, 48, 49
28 to 25, 19 to 12,
8 to 5, 62 to 59
1
2
64
63
53
54
52
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
FB
A
P0 to P19
INT
HS/CS
VS
FIELD/DE
SDATA
SCLK
ALSB
IN
1 to A
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
SFL/SYNC_OUT
IN
DVDDIO
DVDDIO
6
HS/CS
DGND
DGND
P15
P14
P13
P12
P10
P11
INT
P9
P8
P7
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Type
G
G
P
P
P
P
I
I
O
O
O
O
O
I/O
I
I
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
1
Figure 2. Pin Configuration
Description
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
Analog Video Input Channels.
Video Pixel Output Port. Refer to Table 10 for output configuration modes.
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
Vertical Synchronization Output Signal (SDP and CP Modes).
Field Synchronization Output Signal (All Interlaced Video Modes). This pin also
can be enabled as an data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
I
I
This pin selects the I
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
2
2
Rev. 0 | Page 9 of 20
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
ADV7181C
(Not to Scale)
TOP VIEW
2
C address for the ADV7181C control and VBI readback
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
A
A
NC
CAPC2
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
A
A
FB
NC
IN
IN
IN
IN
IN
5
4
3
2
1
ADV7181C