ADV7150LS135 AD [Analog Devices], ADV7150LS135 Datasheet - Page 18

• Manufacturer Part Number: ADV7150LS135
• Description: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
• Manufacturer: AD [Analog Devices]

ADV7150
Data is read from the color palette by first writing to the address
register of the color palette location to be read. The MPU per-
forms three successive read cycles from each of the red, green
and blue locations (10-bit or 8-bit) of the RAM. An internal
pointer moves from red to green to blue after each read is com-
pleted. This pointer is reset to red after a blue read or whenever
the address register is written. The address register then auto-
matically increments to point to the next RAM location, and a
similar red, green and blue palette read sequence is performed.
The address register resets to 00H following a blue read cycle of
color palette RAM location FFH.
REGISTER
ADDRESS
(A15–A0)
0AH
0BH
* THIS REGISTER IS READ ONLY.
A READ CYCLE WILL RETURN ZEROS "00".
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
REGISTER
ADDRESS
SYNC, BLANK & I
TEST REGISTER
ID REGISTER (READ ONLY)
PIXEL MASK REGISTER
COMMAND REGISTER 1
COMMAND REGISTER 2
COMMAND REGISTER 3
RESERVED* (READ ONLY)
RESERVED* (READ ONLY)
RESERVED* (READ ONLY)
REVISION REGISTER
(A7–A0)
PIXEL TEST REGISTER
DAC TEST REGISTER
ADDR
CE
C1 = 1
C0 = 0
R
R
Figure 28. Internal Register Configuration and Address Decoding
REGISTERS
CONTROL
R/W
G
G
REGISTER
C0
MODE
(MR1)
Figure 27. MPU Port and Register Configuration
PLL
C1
B
B
PIXEL MASK
REGISTERS
REGISTER
REGISTER
TEST
CONTROL REGISTERS
ID
ADDRESS REGISTER
MODE REGISTER
D9 – D0
(MR17–MR10)
MPU PORT
(A7–A0)
10 (8+2)
REGISTERS
COMMAND
(CR1–CR3)
REGISTER
REVISION
–18–
POINTS TO LOCATION
CORRESPONDING TO
ADDRESS REG (A7–A0)
Register Accesses
The MPU can write to or read from all of the ADV7150s regis-
ters. C0 and C1 determine whether the Mode Register or Ad-
dress Register is being accessed. Access to these registers is
direct. The Control Registers are accessed indirectly. The
Address Register must point to the desired Control Register.
Figure 28 along with the 8-bit and 10-bit Interface Truth Tables
illustrate the structure and protocol for device communication
over the MPU port.
C1 = 1
C0 = 1
C1 = 0
C0 = 0
PALETTES
DATA TO
REGISTER
RED
REGISTER
(R9–R0)
30
RED
REGISTER
COLOR REGISTERS
LOOK-UP TABLE RAM
GREEN
ADDRESS REG = ADDRESS REG + 1
REGISTER
(256 x 30)
(G9–G0)
GREEN
C1 = 0
C0 = 1
REGISTER
BLUE
REGISTER
(B9–B0)
BLUE
REV. A