ADV7129KS AD [Analog Devices], ADV7129KS Datasheet - Page 15

• Manufacturer Part Number: ADV7129KS
• Description: 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL
• Manufacturer: AD [Analog Devices]

The ADV7129 is a highly integrated circuit containing both
precision analog and high speed digital circuitry. It has been
designed to minimize interference effects on the integrity of the
analog circuitry by the high speed digital circuitry. It is impera-
tive that these same design and layout techniques be applied to
the system level design such that high speed, accurate perfor-
mance is achieved. The “Recommended Analog Circuit Layout”
(see Figure 12) shows the analog interface between the device and
monitor.
The layout should be optimized for lowest noise on the ADV7129
power and ground lines by shielding the digital inputs and pro-
viding good decoupling. The lead length between groups of V
and GND pins should by minimized so as to minimize inductive
ringing.
Ground Planes
The ground plane should encompass all ADV7129 ground pins,
voltage reference circuitry, power supply bypass circuitry for the
ADV7129, the analog output traces, and all the digital signal
traces leading up to the ADV7129. The analog ground plane
should be separated from the system ground plane by a ferrite
bead.
Power Planes
The ADV7129 and any associated analog circuitry should have its
own power plane, referred to as the analog power plane (V
This power plane should be connected to the regular PCB power
plane (V
should be located within three inches of the ADV7129.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7129 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable opera-
tion, to reduce the lead inductance. Best performance is obtained
with 0.1 F ceramic capacitor decoupling. Each group of V
pins on the ADV7129 must have at least one 0.1 F decoupling
capacitor to GND. These capacitors should be placed as close
as possible to the device.
It is important to note that while the ADV7129 contains cir-
cuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
REV. 0
CC
) at a single point through a ferrite bead. This bead
BOARD DESIGN AND LAYOUT CONSIDERATIONS
AA
).
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APPENDIX I
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–15–
the designer should pay close attention to reducing power
supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7129 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7129 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should
be connected to the regular PCB power plane (V
not the analog power plane.
Analog Signal Interconnect
The ADV7129 should be located as close as possible to the
output connectors to minimize noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane,
and not the analog power plane, to maximize the high fre-
quency power supply rejection.
Digital Inputs, especially Pixel Data Inputs and clocking
signals (LOADOUT, LOADIN, etc.) should never overlay
any of the analog signal circuitry and should be kept as far
away as possible.
For best performance, the analog outputs should each have
a 50
should be placed as close as possible to the ADV7129 so as
to minimize reflections.
There are a number of precautions that the user can take to
minimize the effects of data feedthrough.
a. Apply external filtering to the DAC outputs.
b. Reduce input voltage risetime. From experiments, it has
c. Reduce input voltage swing. A reduction from 5 V to 3 V
d. Use series resistors on the pixel inputs (e.g., 100 ).
e. The part can be run at 2 DAC current levels as shown
been seen that a reduction from 2 ns to 4 ns gives signifi-
cant improvement.
gives significant improvement.
in the DAC output. The differential outputs can then be
connected through a differential to single balun trans-
former to eliminate common-mode noise. A phase split-
ter should be used to reduce the 2 levels to 1 at the
monitor end.
load resistor connected to GND. These resistors
ADV7129
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